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AhmedAalaaa / 32-point-FFT-Verilog-design-based-DIT-butterfly-algorithm

This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clock domains and time-shared design
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Error index in image 'butterfly diagram' #1

Open xulu199705 opened 3 weeks ago

xulu199705 commented 3 weeks ago

The data x[2] is calculated with x[2+N/2]=x[2+16]=x[18], instead of x[14].

CleanShot_AhmedAalaaa32-point-FFT-Verilog-design-based-DIT-butterfly-algorithm This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clock domains and time-shar@2x

AhmedAalaaa commented 1 week ago

Yes, this is correct. I should update the diagram accordingly. Thank you.