Poster Creation

[Akilan1999]

This issue discusses on creating poster for the CHERI all hands meeting. The issues the list of Todos to look into:

• [x] Creating overview Structure.
• [x] Create template for the Poster.
• [x] Finalise the abstract.

[Akilan1999]

Feedback received from Hans-Wolfgang, poster_ANNOT.pdf

Points to address

• [x] Minor changes in the abstract and rewriting certain parts of the Abstract.
• [x] Rewrite research question 1 and make the research really specific.
• [x] Redraw diagram for experiment.
• [x] Create space for references.
• [x] Fix incomplete sentense in RangeTLB.
• [x] Strip Du sentence if it's not needed.
• [x] Rewrite last para RangeTLB.

[Akilan1999]

Set new tasks for the Poster recreation:

• Draw new diagrams for the Poster (Changes proposed by Rob).

[Akilan1999]

Changes by Rob Stewart:

Abstract

"Capability-based addressing in the CHERI architecture is designed to improve hardware-level system security. These security guarantees can degrade runtime performance due to increased L1 TLB misses [cite jeremy paper]. Our aim is to achieve capability-based security at zero performance cost. We will use fat pointers to simplify and implement a recently proposed range TLB scheme [cite flexpointer], with the goal of reducing L1 TLB misses and page-walks for memory-intensive CHERI workloads."

Idea box

How about a "Our Idea" box, with an argumentation sequence (written by you as a paragraph) could be:

1. Range translation is the process of , e.g. RMM [cite].

2. Recent work on FlexPointer [cite] extended RMM .

3. In the absence of fat pointers, their Range TLB was its own data structure in memory.

4. We use fat pointers to simplify the implementation of Range TLB by using .

5. We believe this simplified will <state very clearly and succinctly why you think step 4 will result in better performance than FlexPointer.

   alternatively, if you think it's not about beating FlexPointer but instead making CHERI faster in purecap mode, then...

6. We hope to reproduce the FlexPointer results of reducing L1 misses and page walks, to remove recently observed for performance degredation -- the cost of hardware-level security.

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Research Questions

RQ1) Can L1 misses and page-walks be reduced for memory intensive CHERI workloads?

RQ2) Is it possible to implement a simple Range TLB scheme with XX bits using region of a fat pointer?

RQ3) Would this Range TLB scheme improve the runtime efficiency of a memory allocator compared to state-of-the-art allocators on CHERI?

RQ4) Can capability-base addressing provide security guarantees at zero runtime performance cost?