ERROR: Module `\cpu_mem' referenced in module `\cpu' in cell `\mem' is not part of the design

AleksandarKostovic / Riscy-SoC

Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog

MIT License

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ERROR: Module `\cpu_mem' referenced in module `\cpu' in cell `\mem' is not part of the design #4

Open xdnf opened 5 years ago

xdnf commented 5 years ago

yosys -p 'synth_ice40 -top top -json top.json' top.v .... .... .... 2.2.1. Analyzing design hierarchy.. Top module: \top Used module: \timer Used module: \uart Used module: \ram Used module: \cpu Used module: \bus_arbiter Used module: \sync ERROR: Module \cpu_mem' referenced in module\cpu' in cell `\mem' is not part of the design.

AleksandarKostovic commented 5 years ago

I am aveare of the issue, i should have opened that myself.

If i find time i will defenetly work to fix it. However if you try to fix it i would be very pleased to merge the changes.

GiacintoCifelli commented 4 years ago

Hi! It goes over this issue with the following changes in cpu.v:

-    cpu_hazard_unit hazard_unit (
+    hazard_unit hazard_unit (

-    cpu_fetch fetch (
+    fetch fetch (

-    cpu_decode decode (
+    decode decode (

-    cpu_execute execute (
+    execute execute (

-    cpu_mem mem (
+    mem mem (

AleksandarKostovic commented 4 years ago

Hi! It goes over this issue with the following changes in cpu.v:
-    cpu_hazard_unit hazard_unit (
+    hazard_unit hazard_unit (

-    cpu_fetch fetch (
+    fetch fetch (

-    cpu_decode decode (
+    decode decode (

-    cpu_execute execute (
+    execute execute (

-    cpu_mem mem (
+    mem mem (
I have submitted the changes. Please try now :smiley:

Saad525 commented 3 years ago

Hi @AleksandarKostovic , I am having same issue while synthesizing my design on Yosys. Changed the instance name as same as submodule name but still getting this error ERROR: Module '\my_mod' referenced in module '\my_top_mod' in cell '\my_mod' is not part of the design Can you please help it out?

Saad525 commented 3 years ago

Never mind. Just figured it out. Included file in project, now it works.

Superstite commented 3 years ago

Hi @Saad525 . I am having the same issue. Can you please tell me what your solution is? Thanks in advance.

Saad525 commented 3 years ago

@Superstite i think it was resolved by including that file (the module of which is instantiated) in top file. `include "your_file_name.v"

Superstite commented 3 years ago

@Superstite i think it was resolved by including that file (the module of which is instantiated) in top file. `include "your_file_name.v"

Hi, thanks @Saad525.