Closed dpc closed 6 years ago
I am aware of the lock contention issues, it's just that I haven't had time to work on Rust stuff lately. Still, thanks for opening an issue, I'll be sure to look into it at some point.
Using a #[repr(align(64))] pub struct CacheLineAtomicBool(AtomicBool); [CacheLineAtomicBool; 1024]
might be enough to fix this, but I don't recall if 64-byte alignment is supported.
Fixed in 0.4.0
Nice, thanks!
I was just looking through this library (thanks for your work!) and I'm not sure if you are aware that most probably on most architectures the fallback array
static SPINLOCKS: [AtomicBool; 1024] = array![ATOMIC_BOOL_INIT; 1024];
, might be less effective than 1024-ways.Typically the locking granularity is the the cacheline which is 64B on x86. As bools seems to be used in
SPINLOCKS
, each 64 consecutive entries inSPINLOCKS
will occupy same cacheline so they will not be accessible on different CPUs at different times. So effectively this 1024-entry array works like a 16-entry one.Sorry to bother you if you were already aware of that (16 seems like decent concurency level anyway). If not you can read more eg here:
https://www.ibm.com/developerworks/aix/library/au-aix-multicore-multiprocessor/ (ctrf+f "array of spinlocks") and generally google "spinlock false sharing".