3 ms speedup for ST7920 and delay for BOARD_3DRAG

[AnHardt]

3 ms speedup for ST7920 and delay for BOARD_3DRAG and saving ~1k memory by limiting the #pragma GCC optimize (3) optimisation to ultralcd_st7920_u8glib_rrd.h and unrolling the loop in ST7920_SWSPI_SND_8BIT()

Because at least some ST7920 at 3DRAG and/or K8200 boards need a slower timing they get a bit more delays.

[Roxy-3D]

Needs tests and feedback! Are the delays right? Please experiment with longer or shorter delays. And give feedback.

Agreed we need to test and provide feedback. Is it possible to scientifically calculate what the delay should be? That would make me more comfortable because right now it feels like we are guessing. (But THANKS!!!!!)

[AnHardt]

@Roxy-3DPrintBoard and others From the data sheets:

4,5V TSCYC Serial clock cycle Pin E 400 - - ns TSHW SCLK high pulse width Pin E 200 - - ns TSLW SCLK low pulse width Pin E 200 - - ns TSDS SID data setup time Pins RW 40 - - ns TSDH SID data hold time Pins RW 40 - - ns TCSS CS setup time Pins RS 60 - - ns TCSH CS hold time Pins RS 60 - - ns

2.7V //Voltage is time critical !!! TSCYC Serial clock cycle Pin E 600 - - ns TSHW SCLK high pulse width Pin E 300 - - ns TSLW SCLK low pulse width Pin E 300 - - ns TSDS SID data setup time Pins RW 40 - - ns TSDH SID data hold time Pins RW 40 - - ns TCSS CS setup time Pins RS 60 - - ns TCSH CS hold time Pins RS 60 - - ns

1 = 62.5 ns (16MHz) = 50 ns (20MHz) 2 = 125 ns (16MHz) = 100 ns (20MHz) 3 = 187.5 ns (16MHz) = 150 ns (20MHz) 4 = 250 ns (16MHz) = 200 ns (20MHz) 5 = 312.5 ns (16MHz) = 250 ns (20MHz) 6 = 375 ns (16MHz) = 300 ns (20MHz)

Commented assembler stub:

//WRITE(ST7920_CLK_PIN,0);
    cbi 0x2,1    ; ,                //2 ;CLK low

//WRITE(ST7920_DAT_PIN,val&0x80);
    in r18,__SREG__  ;  _sreg,      //1 !1
    sbrc r24,7   ;  val,            //1-3
    rjmp .L19    ;                  //2 !4       .L19
    cli                             //1 !5       cli
    lds r25,258  ;  D.18251,        //2 !7       lds r25,258     ;  D.18251,
    andi r25,lo8(-2)     ;  D.18251,//1 !8   
    sts 258,r25  ; , D.18251        //2 !9-10    sts 258,r25     ; , D.18251  ; DAT set
    out __SREG__,r18     ; , _sreg  //1 !10-11   out __SREG__,r18    ; , _sreg       //no nop needed
                                    //2 !2       rjmp .L3    ; 
//val<<=1;
.L3
    lsl r24  ;  val                 //1 !1-3

//WRITE(ST7920_CLK_PIN,1);   
    sbi 0x2,1    ; ,                //2 !3-5 ; CLK high //no nop needed

//WRITE(ST7920_CLK_PIN,0);
    cbi 0x2,1    ; ,                //2 !2 ; CLK low  2*nop needed for 16MHz and 20MHz 
                                                      to fulfill the specs for 4.5V.
                                                      but many hardware is faster
... 

That could mean the 3DRAG provides a bit less voltage to the display than other boars and therefore needs a somewhat relaxed timing.

[Roxy-3D]

Thank You so much for the Scientific study! I can't help but note that if we put 32-bit support into place, this problem is going to get worse for two reasons. First the processors are faster. But I think most of those processors are running on 3.3 volts which means the timing gets worse on the display.

I guess we will deal with that when the time comes.

[AnHardt]

I'm not to much in sorrow about the ARM processors. We could use the original u8glib device. For the AVRs it's ugly slow, compared to ours. But if we have enough processing power ...

[AnHardt]

Saved an other 'nop' by shifting the left shift into the high phase.