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AndrewNolte / vscode-system-verilog

HDL support for VS Code
MIT License
17 stars 1 forks source link

Syntax highlighting error in module declaration #2

Closed terrywwgit closed 1 month ago

terrywwgit commented 6 months ago

Describe the bug When the variable type is declared in the module declaration port list, the last port name is not colored correctly, the name is the same color as the port type.

Environment (please complete the following information):

Steps to reproduce Steps to reproduce the behavior:

  1. create module declaration
  2. terminate last port line with newline

output fsk_sym_o, output fsk_sym_n_o );

if the ");" is moved to the end of the port line "output fsk_sym_n_o);" the problem does not occur.

Log Attach the log generated while following the above steps

Expected behavior port type and name should have different color.

Actual behavior port name is same as port type

Additional context Add any other context about the problem here.

AndrewNolte commented 5 months ago

Thanks for the report. I've noticed a lot of these too, and they were common bug reports on upstream. I think I might copy in the config from https://github.com/eirikpre/VSCode-SystemVerilog, however In my opinion it makes the colors a bit weird, even though they are often (I'm assuming) more correct. It looks like they copied these on upstream.

I'm going to try to find some time to play around with these but it's not a huge priority to me atm. If anyone's interested in experimenting, it's the tmLanguage files, more info at https://code.visualstudio.com/api/language-extensions/syntax-highlight-guide

AndrewNolte commented 2 months ago

I updated the syntax highlighting in the recent update, do you want to check if this is still an issue?

terrywwgit commented 2 months ago

Yes, it may be a little bit. I have a tapeout thursday, so real busy and avoiding environment changes.

On Mon, Aug 19, 2024 at 3:52 PM Andrew Nolte @.***> wrote:

I updated the syntax highlighting in the recent update, do you want to check if this is still an issue?

— Reply to this email directly, view it on GitHub https://github.com/AndrewNolte/vscode-system-verilog/issues/2#issuecomment-2297648801, or unsubscribe https://github.com/notifications/unsubscribe-auth/BH4EKTYQQDFDQAR75JW6R43ZSJZKRAVCNFSM6AAAAABH7B6GFSVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMZDEOJXGY2DQOBQGE . You are receiving this because you authored the thread.Message ID: @.***>

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terrywwgit commented 1 month ago

No longer an issue. I am now running the latest code.