AndrewNolte / vscode-system-verilog

HDL support for VS Code
MIT License
11 stars 1 forks source link

[BUG] Verible format fails #9

Closed gtaylormb closed 2 weeks ago

gtaylormb commented 4 weeks ago

Environment

Steps to reproduce:

Logs: (Get logs from Output > verilog)

2024-08-14 15:11:29.047 [info] [svFormat] formatting /home/gtaylor/git/fpga/src/clock_crossing/two_stage_synchronizer.sv
2024-08-14 15:11:29.047 [info] [svFormat] [verible] Temp file created at:/tmp/verible-verilog-format-c04d7d624381cefe245a29da3e69dfad.tmp.sv
2024-08-14 15:11:29.047 [info] [svFormat] [verible] Executing command: /opt/verible/bin/verible-verilog-format  --inplace /tmp/verible-verilog-format-c04d7d624381cefe245a29da3e69dfad.tmp.sv
2024-08-14 15:11:29.048 [error] [svFormat] [verible] Error: Command failed: /opt/verible/bin/verible-verilog-format  --inplace /tmp/verible-verilog-format-c04d7d624381cefe245a29da3e69dfad.tmp.sv
<empty-filename>: No such file or directory
AndrewNolte commented 3 weeks ago

I've seen this before actually, and I'm not sure what causes it. I can experiment with having verible do the in-place formatting instead of creating the temporary file. That part wasn't written by me, but I assume they did it because not all formatters support inplace formatting.

AndrewNolte commented 3 weeks ago

Contributions are welcome too! I don't think this should be too difficult for a starter task

AndrewNolte commented 2 weeks ago

Should be fixed in 0.9.17, lmk if it works for you