Error with modules

[Lucas-fm1]

Hi, nice project you got there!

I am trying to run the code with basic tests, to further verify using UVM since I'm currently working with the tool. However, when running only the RTL in Xcelium to detect any sintax error, some messages appear and to me looks like some pieces of code you used are from [standard models (I believe its clock gating).

Can you help me with this issue?

[Angela-WangBo]

Hi Lucas,

Thanks for your interest in my previous project, The highlighted part is an SRAM IP that was generated from a memory compiler from TSMC. Hope it clarifies.

Thanks Wang Bo Assistant Professor Lead, Electronic Design Lab Singapore Univ. of Technology and Design https://sites.google.com/view/bowang/home

On 16 Mar 2024, at 5:42 AM, Lucas Farias @.**@.>> wrote:

External Email – Do not click on any links or open any attachments from an unknown sender.

Hi, nice project you got there!

I am trying to run the code with basic tests, to further verify using UVM since I'm currently working with the tool. However, when running only the RTL in Xcelium to detect any sintax error, some messages appear and to me looks like some pieces of code you used are from [standard models (I believe its clock gating).

Can you help me with this issue?

bugShenjing.PNG (view on web)https://github.com/Angela-WangBo/Shenjing-RTL/assets/58792177/b38579bf-c74b-4169-9f97-c5c15ee6a0bd

— Reply to this email directly, view it on GitHubhttps://github.com/Angela-WangBo/Shenjing-RTL/issues/1, or unsubscribehttps://github.com/notifications/unsubscribe-auth/AOTY3JBIZFQV5Y76CBLQAFDYYNTKVAVCNFSM6AAAAABEYWINAKVHI2DSMVQWIX3LMV43ASLTON2WKOZSGE4DSNJQHE2TGNI. You are receiving this because you are subscribed to this thread.Message ID: @.***>

[Lucas-fm1]

Thanks for the info! Can I generate this memories by my own? If so, where can I find such generator? It would be nice to follow the same flow you guys did.

Obter o Outlook para Androidhttps://aka.ms/AAb9ysg

---

From: Angela-WangBo @.> Sent: Saturday, March 16, 2024 6:48:33 AM To: Angela-WangBo/Shenjing-RTL @.> Cc: Lucas Farias Martins @.>; Author @.> Subject: Re: [Angela-WangBo/Shenjing-RTL] Error with modules (Issue #1)

Hi Lucas,

Thanks for your interest in my previous project, The highlighted part is an SRAM IP that was generated from a memory compiler from TSMC. Hope it clarifies.

Thanks Wang Bo Assistant Professor Lead, Electronic Design Lab Singapore Univ. of Technology and Design https://sites.google.com/view/bowang/home

On 16 Mar 2024, at 5:42 AM, Lucas Farias @.**@.>> wrote:

External Email – Do not click on any links or open any attachments from an unknown sender.

Hi, nice project you got there!

I am trying to run the code with basic tests, to further verify using UVM since I'm currently working with the tool. However, when running only the RTL in Xcelium to detect any sintax error, some messages appear and to me looks like some pieces of code you used are from [standard models (I believe its clock gating).

Can you help me with this issue?

bugShenjing.PNG (view on web)https://github.com/Angela-WangBo/Shenjing-RTL/assets/58792177/b38579bf-c74b-4169-9f97-c5c15ee6a0bd

— Reply to this email directly, view it on GitHubhttps://github.com/Angela-WangBo/Shenjing-RTL/issues/1, or unsubscribehttps://github.com/notifications/unsubscribe-auth/AOTY3JBIZFQV5Y76CBLQAFDYYNTKVAVCNFSM6AAAAABEYWINAKVHI2DSMVQWIX3LMV43ASLTON2WKOZSGE4DSNJQHE2TGNI. You are receiving this because you are subscribed to this thread.Message ID: @.***>

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[Angela-WangBo]

Unfortunately I don’t think you can generate it unless you obtain the compiler from a chip fabrication agent like IMEC or MUSE.

Sent from my iPhone

On 16 Mar 2024, at 8:57 PM, Lucas Farias @.***> wrote:

 External Email – Do not click on any links or open any attachments from an unknown sender.

Thanks for the info! Can I generate this memories by my own? If so, where can I find such generator? It would be nice to follow the same flow you guys did.

Obter o Outlook para Androidhttps://aka.ms/AAb9ysg

---

From: Angela-WangBo @.> Sent: Saturday, March 16, 2024 6:48:33 AM To: Angela-WangBo/Shenjing-RTL @.> Cc: Lucas Farias Martins @.>; Author @.> Subject: Re: [Angela-WangBo/Shenjing-RTL] Error with modules (Issue #1)

Hi Lucas,

Thanks for your interest in my previous project, The highlighted part is an SRAM IP that was generated from a memory compiler from TSMC. Hope it clarifies.

Thanks Wang Bo Assistant Professor Lead, Electronic Design Lab Singapore Univ. of Technology and Design https://sites.google.com/view/bowang/home

On 16 Mar 2024, at 5:42 AM, Lucas Farias @.**@.>> wrote:

External Email – Do not click on any links or open any attachments from an unknown sender.

Hi, nice project you got there!

I am trying to run the code with basic tests, to further verify using UVM since I'm currently working with the tool. However, when running only the RTL in Xcelium to detect any sintax error, some messages appear and to me looks like some pieces of code you used are from [standard models (I believe its clock gating).

Can you help me with this issue?

bugShenjing.PNG (view on web)https://github.com/Angela-WangBo/Shenjing-RTL/assets/58792177/b38579bf-c74b-4169-9f97-c5c15ee6a0bd

— Reply to this email directly, view it on GitHubhttps://github.com/Angela-WangBo/Shenjing-RTL/issues/1, or unsubscribehttps://github.com/notifications/unsubscribe-auth/AOTY3JBIZFQV5Y76CBLQAFDYYNTKVAVCNFSM6AAAAABEYWINAKVHI2DSMVQWIX3LMV43ASLTON2WKOZSGE4DSNJQHE2TGNI. You are receiving this because you are subscribed to this thread.Message ID: @.***>

— Reply to this email directly, view it on GitHubhttps://github.com/Angela-WangBo/Shenjing-RTL/issues/1#issuecomment-2001931586, or unsubscribehttps://github.com/notifications/unsubscribe-auth/AOARR4J642NOBAMMG6L2U73YYQIPDAVCNFSM6AAAAABEYWINAKVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMZDAMBRHEZTCNJYGY. You are receiving this because you authored the thread.Message ID: @.***>

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[Lucas-fm1]

I understand, but thanks anyway for all your help and attention. I'll see what I can do from here, and also hoping we keep in touch. =)

Obter o Outlook para Androidhttps://aka.ms/AAb9ysg

---

From: Angela-WangBo @.> Sent: Saturday, March 16, 2024 12:58:36 PM To: Angela-WangBo/Shenjing-RTL @.> Cc: Lucas Farias Martins @.>; Author @.> Subject: Re: [Angela-WangBo/Shenjing-RTL] Error with modules (Issue #1)

Unfortunately I don’t think you can generate it unless you obtain the compiler from a chip fabrication agent like IMEC or MUSE.

Sent from my iPhone

On 16 Mar 2024, at 8:57 PM, Lucas Farias @.***> wrote:

 External Email – Do not click on any links or open any attachments from an unknown sender.

Thanks for the info! Can I generate this memories by my own? If so, where can I find such generator? It would be nice to follow the same flow you guys did.

Obter o Outlook para Androidhttps://aka.ms/AAb9ysg

---

From: Angela-WangBo @.> Sent: Saturday, March 16, 2024 6:48:33 AM To: Angela-WangBo/Shenjing-RTL @.> Cc: Lucas Farias Martins @.>; Author @.> Subject: Re: [Angela-WangBo/Shenjing-RTL] Error with modules (Issue #1)

Hi Lucas,

Thanks for your interest in my previous project, The highlighted part is an SRAM IP that was generated from a memory compiler from TSMC. Hope it clarifies.

Thanks Wang Bo Assistant Professor Lead, Electronic Design Lab Singapore Univ. of Technology and Design https://sites.google.com/view/bowang/home

On 16 Mar 2024, at 5:42 AM, Lucas Farias @.**@.>> wrote:

External Email – Do not click on any links or open any attachments from an unknown sender.

Hi, nice project you got there!

I am trying to run the code with basic tests, to further verify using UVM since I'm currently working with the tool. However, when running only the RTL in Xcelium to detect any sintax error, some messages appear and to me looks like some pieces of code you used are from [standard models (I believe its clock gating).

Can you help me with this issue?

bugShenjing.PNG (view on web)https://github.com/Angela-WangBo/Shenjing-RTL/assets/58792177/b38579bf-c74b-4169-9f97-c5c15ee6a0bd

— Reply to this email directly, view it on GitHubhttps://github.com/Angela-WangBo/Shenjing-RTL/issues/1, or unsubscribehttps://github.com/notifications/unsubscribe-auth/AOTY3JBIZFQV5Y76CBLQAFDYYNTKVAVCNFSM6AAAAABEYWINAKVHI2DSMVQWIX3LMV43ASLTON2WKOZSGE4DSNJQHE2TGNI. You are receiving this because you are subscribed to this thread.Message ID: @.***>

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[Lucas-fm1]

Hi Angela, it's me again!

I am trying to create a HDL version of the memory used (TS1N28LPB128X64M4SSOR) based on the interface. Is there a open documentation, just to understand how the memory behave with the variables?

[cid:323bf90c-d1b4-4881-9a62-0c01a099ef7d]

---

De: Lucas Farias Martins @.> Enviado: sábado, 16 de março de 2024 09:03 Para: Angela-WangBo/Shenjing-RTL @.>; Angela-WangBo/Shenjing-RTL @.> Cc: Author @.> Assunto: Re: [Angela-WangBo/Shenjing-RTL] Error with modules (Issue #1)

I understand, but thanks anyway for all your help and attention. I'll see what I can do from here, and also hoping we keep in touch. =)

Obter o Outlook para Androidhttps://aka.ms/AAb9ysg

---

From: Angela-WangBo @.> Sent: Saturday, March 16, 2024 12:58:36 PM To: Angela-WangBo/Shenjing-RTL @.> Cc: Lucas Farias Martins @.>; Author @.> Subject: Re: [Angela-WangBo/Shenjing-RTL] Error with modules (Issue #1)

Unfortunately I don’t think you can generate it unless you obtain the compiler from a chip fabrication agent like IMEC or MUSE.

Sent from my iPhone

On 16 Mar 2024, at 8:57 PM, Lucas Farias @.***> wrote:

 External Email – Do not click on any links or open any attachments from an unknown sender.

Thanks for the info! Can I generate this memories by my own? If so, where can I find such generator? It would be nice to follow the same flow you guys did.

Obter o Outlook para Androidhttps://aka.ms/AAb9ysg

---

From: Angela-WangBo @.> Sent: Saturday, March 16, 2024 6:48:33 AM To: Angela-WangBo/Shenjing-RTL @.> Cc: Lucas Farias Martins @.>; Author @.> Subject: Re: [Angela-WangBo/Shenjing-RTL] Error with modules (Issue #1)

Hi Lucas,

Thanks for your interest in my previous project, The highlighted part is an SRAM IP that was generated from a memory compiler from TSMC. Hope it clarifies.

Thanks Wang Bo Assistant Professor Lead, Electronic Design Lab Singapore Univ. of Technology and Design https://sites.google.com/view/bowang/home

On 16 Mar 2024, at 5:42 AM, Lucas Farias @.**@.>> wrote:

External Email – Do not click on any links or open any attachments from an unknown sender.

Hi, nice project you got there!

I am trying to run the code with basic tests, to further verify using UVM since I'm currently working with the tool. However, when running only the RTL in Xcelium to detect any sintax error, some messages appear and to me looks like some pieces of code you used are from [standard models (I believe its clock gating).

Can you help me with this issue?

bugShenjing.PNG (view on web)https://github.com/Angela-WangBo/Shenjing-RTL/assets/58792177/b38579bf-c74b-4169-9f97-c5c15ee6a0bd

— Reply to this email directly, view it on GitHubhttps://github.com/Angela-WangBo/Shenjing-RTL/issues/1, or unsubscribehttps://github.com/notifications/unsubscribe-auth/AOTY3JBIZFQV5Y76CBLQAFDYYNTKVAVCNFSM6AAAAABEYWINAKVHI2DSMVQWIX3LMV43ASLTON2WKOZSGE4DSNJQHE2TGNI. You are receiving this because you are subscribed to this thread.Message ID: @.***>

— Reply to this email directly, view it on GitHubhttps://github.com/Angela-WangBo/Shenjing-RTL/issues/1#issuecomment-2001931586, or unsubscribehttps://github.com/notifications/unsubscribe-auth/AOARR4J642NOBAMMG6L2U73YYQIPDAVCNFSM6AAAAABEYWINAKVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMZDAMBRHEZTCNJYGY. You are receiving this because you authored the thread.Message ID: @.***>

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[Lucas-fm1]

Hi Angela, it's me again!

I didn't said before, but I'm a master degree student in electrical engineering currently researching on neuromorphic computing. Me and my advisor are thinking in an article using the chip to deploy a network created for the context of SPR sensors.

Do you have a systemverilog testbench, or a framwork avaliable that you used on Shenjing? It would be very helpful.

---

De: Lucas Farias Martins @.> Enviado: terça-feira, 16 de abril de 2024 12:52 Para: Lucas Farias Martins @.> Assunto: RE: [Angela-WangBo/Shenjing-RTL] Error with modules (Issue #1)

Hi Angela, it's me again!

I didn't said before, but I'm a master degree student in electrical engineering currently researching on neuromorphic computing. Me and my advisor are thinking in an article using the chip to deploy a network created for the context of SPR sensors.

Do you have a systemverilog testbench, or a framwork avaliable that you used on Shenjing? It would be very helpful.

---

De: Lucas Farias Martins @.> Enviado: quarta-feira, 27 de março de 2024 05:55 Para: Angela-WangBo/Shenjing-RTL @.>; Angela-WangBo/Shenjing-RTL @.> Cc: Author @.> Assunto: RE: [Angela-WangBo/Shenjing-RTL] Error with modules (Issue #1)

Hi Angela, it's me again!

I am trying to create a HDL version of the memory used (TS1N28LPB128X64M4SSOR) based on the interface. Is there a open documentation, just to understand how the memory behave with the variables?

[cid:323bf90c-d1b4-4881-9a62-0c01a099ef7d]

---

De: Lucas Farias Martins @.> Enviado: sábado, 16 de março de 2024 09:03 Para: Angela-WangBo/Shenjing-RTL @.>; Angela-WangBo/Shenjing-RTL @.> Cc: Author @.> Assunto: Re: [Angela-WangBo/Shenjing-RTL] Error with modules (Issue #1)

I understand, but thanks anyway for all your help and attention. I'll see what I can do from here, and also hoping we keep in touch. =)

Obter o Outlook para Androidhttps://aka.ms/AAb9ysg

---

From: Angela-WangBo @.> Sent: Saturday, March 16, 2024 12:58:36 PM To: Angela-WangBo/Shenjing-RTL @.> Cc: Lucas Farias Martins @.>; Author @.> Subject: Re: [Angela-WangBo/Shenjing-RTL] Error with modules (Issue #1)

Unfortunately I don’t think you can generate it unless you obtain the compiler from a chip fabrication agent like IMEC or MUSE.

Sent from my iPhone

On 16 Mar 2024, at 8:57 PM, Lucas Farias @.***> wrote:

 External Email – Do not click on any links or open any attachments from an unknown sender.

Thanks for the info! Can I generate this memories by my own? If so, where can I find such generator? It would be nice to follow the same flow you guys did.

Obter o Outlook para Androidhttps://aka.ms/AAb9ysg

---

From: Angela-WangBo @.> Sent: Saturday, March 16, 2024 6:48:33 AM To: Angela-WangBo/Shenjing-RTL @.> Cc: Lucas Farias Martins @.>; Author @.> Subject: Re: [Angela-WangBo/Shenjing-RTL] Error with modules (Issue #1)

Hi Lucas,

Thanks for your interest in my previous project, The highlighted part is an SRAM IP that was generated from a memory compiler from TSMC. Hope it clarifies.

Thanks Wang Bo Assistant Professor Lead, Electronic Design Lab Singapore Univ. of Technology and Design https://sites.google.com/view/bowang/home

On 16 Mar 2024, at 5:42 AM, Lucas Farias @.**@.>> wrote:

External Email – Do not click on any links or open any attachments from an unknown sender.

Hi, nice project you got there!

I am trying to run the code with basic tests, to further verify using UVM since I'm currently working with the tool. However, when running only the RTL in Xcelium to detect any sintax error, some messages appear and to me looks like some pieces of code you used are from [standard models (I believe its clock gating).

Can you help me with this issue?

bugShenjing.PNG (view on web)https://github.com/Angela-WangBo/Shenjing-RTL/assets/58792177/b38579bf-c74b-4169-9f97-c5c15ee6a0bd

— Reply to this email directly, view it on GitHubhttps://github.com/Angela-WangBo/Shenjing-RTL/issues/1, or unsubscribehttps://github.com/notifications/unsubscribe-auth/AOTY3JBIZFQV5Y76CBLQAFDYYNTKVAVCNFSM6AAAAABEYWINAKVHI2DSMVQWIX3LMV43ASLTON2WKOZSGE4DSNJQHE2TGNI. You are receiving this because you are subscribed to this thread.Message ID: @.***>

— Reply to this email directly, view it on GitHubhttps://github.com/Angela-WangBo/Shenjing-RTL/issues/1#issuecomment-2001931586, or unsubscribehttps://github.com/notifications/unsubscribe-auth/AOARR4J642NOBAMMG6L2U73YYQIPDAVCNFSM6AAAAABEYWINAKVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMZDAMBRHEZTCNJYGY. You are receiving this because you authored the thread.Message ID: @.***>

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