axi_traffic_gen_0 not found

[goodallen]

axi_traffic_gen_0 file not found ? pls add it

[AngeloJacobo]

Hi @goodallen, axi_traffic_gen_0 is part of the testbench for testing the AXI interface. This module can only be generated from Vivado IP generator (IP: AXI Traffic Generator). A blog update for the AXI interface will be added soon and will have the instruction on how to generate this IP. (Blog website: https://www.openiphub.com/)

[goodallen]

thanks a lot，the project really helps me to understand ddr3 protocol，but I’m confused between mc and phy not standard dfi,right?

[AngeloJacobo]

Nice :), more blog updates will be released focusing on the RTL implementation of this UberDDR3. About the PHY, yes that's right, DFI protocol is not used. There is a point to point connection between the controller and PHY, and there is no protocol in between them. First reason was to make it less complicated, and second reason was we do not have a need for this yet since the PHY is still available only for AMD 7-series FPGAs. If in the future updates where the PHY needs to support other FPGA vendors then that might be time to assess if a DFI protocol is needed.

[goodallen]

get! I will try more effort to get a better understanding about DDR3 protocol,like timing parameters,write/read calibration etc,appreciate your UberDDR3 project again👍