Instruction overrun error while trying to use Microblaze with UberDDR3

[nuclearrambo]

When integrating Microblaze with UberDDR3, Vitis throws "Instruction overrun" error after configuring the FPGA. Ideally, the Microblaze fires up and waits at the first breakpoint at start of the program while debugging through Vitis. Its by design that the uberDDR3 writes the entire address space and reads it back as a test procedure after calibration. This makes the RAM inaccessible causing Microblaze to fail. Disabling the read/write test fixed the problem, and I could debug programs on Microblaze just like I did when using MIG. On line 1830, I made the following change state_calibrate <= DONE_CALIBRATE;

[AngeloJacobo]

Hi @nuclearrambo , would it be possible to add a reset logic in Microblaze such that the reset will only be released when UberDDR3 is done calibrating? The built-in self-test is not actually a requirement in the calibration sequence of a DDR3 controller, but having it would add a lot more confidence that UberDDR3 was able to properly calibrate.

By the way, running UberDDR3 on Microblaze sounds interesting, would it possible to share here the working project you had? Maybe we can add yours in the example project demo in this repo.

[nuclearrambo]

I have created a sample project in Vivado 2019.2. I used the project mode so, you may need to modify the IP versions accordingly in the tcl script. Step 1: Create a new project Step 2: Add the "rtl" and "rtl/axi" directories when it asks for sources Step 3: In the tcl console run this "source bd.tcl" This should automatically create the block design. Add the pin constraints based on your board. I had a custom board so my constraints wouldn't be useful here. Note: Rename the bd.txt to bd.tcl

Edit: Links to the bd.tcl and block design pdf. https://github.com/nuclearrambo/UberDDR3/blob/main/bd.tcl https://github.com/nuclearrambo/UberDDR3/blob/main/design_1.pdf