Trying to enable the emulator to simulate privileged arch as well as userspace. In order to implement this, I needed to add:
Support for the Control and Status Registers (CSR) to the CPU
Interrupt handling
This is implemented in the PrivCPU class.
I decided, that adding support for loading elf formatted binaries was also on the menu. This is implemented in the ElfLoader and PrivMMU class. I added a decoder module as well to decode these machine code instructions again.
I added the PrivRV32I instruction set, which uses relative offsets in jump and branch instructions, in order to more easily support loaded binaries. Additionally, the PrivRV32I instruction set supports the CSR instructions.
Trying to enable the emulator to simulate privileged arch as well as userspace. In order to implement this, I needed to add:
This is implemented in the PrivCPU class.
I decided, that adding support for loading elf formatted binaries was also on the menu. This is implemented in the ElfLoader and PrivMMU class. I added a decoder module as well to decode these machine code instructions again.
I added the
PrivRV32Iinstruction set, which uses relative offsets in jump and branch instructions, in order to more easily support loaded binaries. Additionally, thePrivRV32Iinstruction set supports theCSRinstructions.