AntonLydike / riscemu

RISC-V emulator in python
MIT License
48 stars 14 forks source link

Move CSR from priv to non-priv CPU #26

Closed AntonLydike closed 1 year ago

AntonLydike commented 1 year ago

Since we added floating point support, CSR support is technically needed in user mode as well. We have a primitive implementation of CSR in the PrivCPU, we just need to move it (and corresponding instructions) to non-priv CPU

AntonLydike commented 1 year ago

This was implemented in #47 and subsequently released in v2.2.0