search

AntonLydike / riscemu

RISC-V emulator in python
MIT License
48 stars 13 forks source link

Feature m instruction set #48

Closed Joshy-R closed 4 months ago

Joshy-R commented 11 months ago

Length Assertion in JALR instruction was faulty. Implements MULHSU and MULHU. Fixes overflow bug in MULH

AntonLydike commented 11 months ago

Hey! Thanks for these fixes! Do you mind adding a filecheck test that passes now but failed previously? I feel that this would help greatly in improving confidence in the emulation accuracy!

Something like this should do:

// RUN: riscemu -o libc %s | filecheck %s

.text
.globl main
main:
    li a0, 0xabcdefgh...
    mulh a1, a0, a0
    print a1
// CHECK: register a1 contains value ...
    mulhu a1, a0, a0
    print a1
// CHECK-NEXT: register a1 contains value ...
    ret
AntonLydike commented 11 months ago

Hey @Joshy1970, if you need help with this or have any questions, feel free to let me know!

Joshy-R commented 11 months ago

Hey, I got sick but will be working on it in one or two days. Seems straightforward, so I think I don't need help, but thanks for offering, and sorry for being absent for so long

Joshy-R commented 11 months ago

I added the filecheck now. Is there anything else i need to change?

AntonLydike commented 10 months ago

Heya, sorry for the lack of response, we had a busy few weeks and this fell under the table. It looks like you tried to rebase these changes in a weird way, can you try to make the diff a bit smaller?

AntonLydike commented 9 months ago

If you're okay with it I'd give rebasing and cleaning up the conflicts a go myself. Sorry again for letting this slip!