AntonLydike / riscemu

RISC-V emulator in python
MIT License
48 stars 14 forks source link

Add support for flen=64 #49

Closed AntonLydike closed 1 year ago

AntonLydike commented 1 year ago

Currently still missing a lot of the D extension (all except fmadd, fmsub, fnmsub, fnmadd, fadd, fsub, fmul, fdiv, fsqrt, fsgnj, fsgnjn, fsgnjx, fmin, fmax, feq, flt, fle, fld, fsd), missing conversion and move instructions.

This may break some of the float32 stuff, so we should be very careful with this.

Todos:

AntonLydike commented 1 year ago

@superlopuh any instructions you are missing so far?