Closed PythonLinks closed 7 months ago
PythonLinks
commented
11 months ago And one more point. Sorry I forgot it. For many of us we do not know what the RISC-V instruction names mean, so maybe good next to each instruction that you specify would be a one sentence description, saves us looking it up.
And interesting that I this is the first issue on a 4 year old project. Sadly people are just not as interested in small processors as they should be.
AntonMause
commented
7 months ago Hi Py,
thanx for your interest.
execution width XLEN of 16 bit (rv16) is no official standard but after Analog Devices designed a 16 bit reference chip to demonstrate NanoTubes, mine should be legal too.
Don't nix up with "steno/shortform", 16 bit wide instruction, these get decoded to 32 bit wide instruction, executing in the machine XLEN=64 or 32 bit (here 16 bit). (see rv16c) My intention was to build a core around a 18bit DSP slice, so 16 bit was just for simplification.
Well 32KB vs. 64KB, signed vs. unsigned, 2GB vs. 4GB address range, it is all the same as long as you stay within borders. This is where RISC-V default (signed) differs from ARM (unsigned) when extending arguments. So it is safe to assume signed and stay one bit below the maximum, then the wrap around will not beat you.
Yes, trust the number in the readme, the XLEN for the rv16 CPU can scale from 6 or 8 to 16 bit. Utilization may even go below 200 LUT4 for blinking 2 LED only. But this is a bit unfair as unused instruction are not synthesized.
Once again, let the source be with you, reading helps :-) You may find the board files in the board folder. All boards carry Microchip / Microsemi / Actel devices (gen4+5).
Well documentation : like most RV cores this one also is too boring to put notes on :-) Who ever saw a MIPS, MicroBlaze, NIOS, ... core, sees the flow, hey 2 pages of VHDL. Check RISC-V for documentation on RISC-V.
First thanks for doing this.
I have lots of small comments.
We are just learning about RISC-V in school. the 16 bit stuff is small and therefore efficient and interesting.
Some clarification at the top would be helpful. I think that RISC-V does not specify a 16 bit processor, but they do specify a 16 bit instruction set, and the instructions. So I guess they specify a 16 bit processor. Some explanation of the context would be hepful.
Somewhere you mentioned 32K. I thought that 2**16 comes to 64 K addresses. What am I missing?
What board are you synthesizing this on? How many luts does it take. Are those 4 or 6 bit luts? For small cpus, FPGA resources consumed is a critical number. I would like to quote your numbers.
What frequency is it running at?
Links to relevant resources would also be appreciated.
So thanks for all that you have done so far. And yes, I do understand that you are doing this on a volunteer basis.
I hope that helps.