Open rsaxvc opened 1 year ago
Have you tried compiling with that option? How does it effect code-size?
@rsaxvc definately worth trying, do you need help benchmarking this?
There's two parts here, switching CMSIS and switching ArduPilot.
@magicrub , adding -falign-loops=4 to just the ArduPilot files seems to add only +20B on the KakuteH7 copter 4.4 build. I wonder if GCC is tending towards aligning most loops already on M7. Haven't rebuilt an M4 with CMSIS yet.
@tridge, help benchmarking would be great.
CMSIS might also benefit from -falign-functions like the rest of the AP codebase, which is currently aligning functions at 16B.
I built a few boards to look at the differences in codespace vs instructions. In short, I don't think this is worth looking into for the main ArduPilot codebase. Each -falign=4 build added:
Usually this impacts the following functions(which vary per build):
I don't think this may not be worth the effort of profiling for the bulk of ArduPilot, because UpdateFilter() seems like the only thing possibly useful for tuning, but that loop is large enough that the penalty cycle would always be a small part.
I'll probably pick this up for the CMSIS stuff when I get back to building that from source.
Feature request
Is your feature request related to a problem? Please describe. I'd like to suggest a potential small optimization for Cortex-M3 and M4, possibly M7.
Describe the solution you'd like This ticket tracks the testing and tuning of different loop alignment options for ArduPilot and CMSIS. I'd like feedback on proposed loop tuning.
Describe alternatives you've considered An alternative would be to keep it as-is, which results in no additional loop padding(wasted space).
Platform [ ] All [ ] AntennaTracker [X] Copter [ ] Plane [ ] Rover [ ] Submarine
Additional context On several M4 devices, I've run into a per-iteration penalty cycle for loops that start with a 32-bit instruction that is only 16-bit aligned. I've noticed a few places this occurs in CMSIS in ArduPilot, and wanted to suggest considering tuning the -falign-loops=4 parameter, which would result in adding a narrow NOP(1 loop entry overhead) just before each unaligned loop(even those starting with a narrow instruction). Here's an example from CMSIS:
I suspect M7 has a 64-bit or wider fetch interface, so this would may impact it when a 32-bit instruction stradles two instruction fetches. And Cortex-M7 has a branch predictor, so may not suffer from this as often as the M4.