ALU is a name conflict with GOWIN FPGAs

Arlet / verilog-6502

A Verilog HDL model of the MOS 6502 CPU

http://c-scape.nl/arlet/fpga/6502/

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Open stacksmith opened 3 months ago

stacksmith commented 3 months ago

Both the native GOWIN toolchain and yosys/apycula use the symbol ALU to designate internal logic units.

I just made it xALU in module definition and instantiation, but you may want something more creative...