Open chili-chips-ba opened 1 month ago
Thanks for the interest. I browsed through some of the links you've provided. I don't see a crisp set of rules that can be lint-checked. CDC verification is ofcourse a wider problem involving multitude of techniques and looks like that cdc_snitch is a good start. What exactly do you have in mind for source code level Verilog/SV (or even VHDL) lint checks w.r.t CDC?
Here are some basic conceptual rules. I am looking for more concrete ones to implement via PySlint.
clk_a
, clk_b
).... you may also want to take a look at this @obruendl repo with descriptions of common CDC scenarios and library modules for handling them:
For starters, we could check the scenarios that mainstream commercial tools address:
There is also this open-source project that can be taken for reference:
Verilator CDC Request Yosys CDC Request Slang CDC Request