Open mungalched opened 3 hours ago
module adder #( parameter WIDTH = 32 )( input logic [WIDTH-1:0] a, b, output logic [WIDTH-1:0] result );
always_comb begin result <= '{default:0}; // This line will cause the syntax error in Verilog-2005 end
endmodule
https://github.com/YosysHQ/yosys/issues/792
mungalched
commented
2 hours ago mungalched
commented
2 hours ago
module adder #( parameter WIDTH = 32 )( input logic [WIDTH-1:0] a, b, output logic [WIDTH-1:0] result );
endmodule