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AsFigo / yoYoLint

SystemVerilog RTL Linter for YoSys
https://www.asfigo.com
MIT License
4 stars 1 forks source link

Yosys does not support multi-dimensional parameters #16

Open dpln opened 4 hours ago

dpln commented 4 hours ago

module m ; parameter logic [31:0] CHIPS [0:1] = '{ 32'h6077AE6C, 32'h4E077AE6}; endmodule