Yosys does not support multi-dimensional parameters

[dpln]

module m ; parameter logic [31:0] CHIPS [0:1] = '{ 32'h6077AE6C, 32'h4E077AE6}; endmodule

[ajeethakv]

• Rule Suggestion: Detect multi-dimensional parameter declarations in SystemVerilog.
• Purpose: Yosys does not support multi-dimensional parameters, leading to synthesis incompatibility.
• Expected Outcome: Flag multi-dimensional parameter usage to ensure Yosys compatibility by enforcing single-dimensional parameters.

[sajanalulu]

https://github.com/AsFigo/yoYoLint/blob/main/sv_tests/synth_tests/test_16.sv