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AsFigo / yoYoLint

SystemVerilog RTL Linter for YoSys
https://www.asfigo.com
MIT License
4 stars 1 forks source link

yosys does not support arrays as inputs to modules #17

Open dpln opened 4 hours ago

dpln commented 4 hours ago

module m (input [1:0] initial_state [0:31]);  endmodule