AsFigo / yoYoLint

SystemVerilog RTL Linter for YoSys
https://www.asfigo.com
MIT License
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genvar inside for loop not supported #5

Open ajeethakv opened 1 month ago

ajeethakv commented 1 month ago
module top(output integer o);
   parameter integer RhoOffset = 2;
   // parameter integer RhoOffset [2]  = '{0, 1};
   // genvar i, y;
   for (genvar i = 0 ; i < 1 ; i++) begin
      for (genvar y = 0 ; y < 1 ; y++) begin
         assign o = RhoOffset[1];
      end
  end
endmodule