Segunda fase - codificación del HDL

[AustinMV]

Descripción

Se muestra los códigos realizados de cada sección del desarrollo del circuito decodificador de Gray

[AustinMV]

Código de Gray a binario

//decodificación del código de gray, de contador binario a código de gray
module gray_a_binario(gray,bin);

input [3:0] gray;
output [3:0] bin;

assign gray[3]=bin[3];
assign gray[2]=bin[3]^bin[2];
assign gray[1]=bin[2]^bin[1];
assign gray[0]=bin[1]^bin[0];

endmodule

//decodificación del código de gray, de contador binario a codigo de gray
module gray_a_binario_tb();

reg [3:0] gray;
wire [3:0] outgray, outbin;

gray_a_binario dut1 (.bin(in), .gray(outgray));
gray_a_binario dut2 (.gray(in), .bin(outbin));

initial begin
in=4'b0000;
#10

in=4'b0110;
#10

in=4'b1011;
#10

$stop;
end
endmodule

[AustinMV]

Código de encendido de leds de la NEXYS 4 y refrescamiento de las luces al menos cada 500 ms

 //encendido de LEDS en la NEXYS4
module disenodigital(
input wire [3:0] sw,
output wire [6:0] a_to_g,
output wire [7:0] an,
output wire dp
    );

assign an=8'b11111110; //habilitación de dígitos
assign dp=1; //
hex7seg D1(.x(sw), .a_to_g(a_to_g)); //hexadecimal a 7 segmentos

endmodule

module oneHz_generator(
    input clk_100MHz,
    output clk_1Hz
    );

    reg [25:0] counter_reg;
    reg clk_out_reg = 0;

    always @(posedge clk_100MHz) begin
        if(counter_reg==49999999) begin
            counter_reg <= 0;
            clk_out_reg <= ~clk_out_reg;
        end
        else
            counter_reg <= counter_reg +1;
    end

    assign clk_1Hz = clk_out_reg;

endmodule 

[JoseDavidL]

Código decodificado en display de 7 segmentos.

// Código decodificado en display de 7 segmentos.
// función hexadecimal a 7 segmentos
module hex7seg(
    input wire [3:0]x,
    output reg [6:0]a_to_g //conectado de a a g
    );

 always@(*)
 begin

 //Casos en los interruptores para mostral los números
    case(x)
    0: a_to_g = 7'b0000001;
    1: a_to_g = 7'b1001111;
    2: a_to_g = 7'b0010010;
    3: a_to_g = 7'b0000110;
    4: a_to_g = 7'b1001100;
    5: a_to_g = 7'b0100100;
    6: a_to_g = 7'b0100000;
    7: a_to_g = 7'b0001111;
    8: a_to_g = 7'b0000000;
    9: a_to_g = 7'b0000100;
    'hA: a_to_g = 7'b0001000;
    'hB: a_to_g = 7'b1100000;
    'hC: a_to_g = 7'b0110001;
    'hD: a_to_g = 7'b1000010;
    'hE: a_to_g = 7'b0110000;
    'hF: a_to_g = 7'b0111000;
    default: a_to_g = 7'b0000001;
 endcase
 end endmodule    

// distribución de los pines display de 7 segmentos
set_property IOSTANDARD LVCMOS33 [get_ports {a_to_g[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_to_g[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_to_g[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_to_g[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_to_g[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_to_g[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a_to_g[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports dp]
set_property PACKAGE_PIN J15 [get_ports {sw[0]}]
set_property PACKAGE_PIN L16 [get_ports {sw[1]}]
set_property PACKAGE_PIN M13 [get_ports {sw[2]}]
set_property PACKAGE_PIN R15 [get_ports {sw[3]}]
set_property PACKAGE_PIN H15 [get_ports dp]
set_property PACKAGE_PIN T10 [get_ports {a_to_g[0]}]
set_property PACKAGE_PIN R10 [get_ports {a_to_g[1]}]
set_property PACKAGE_PIN K16 [get_ports {a_to_g[2]}]
set_property PACKAGE_PIN K13 [get_ports {a_to_g[3]}]
set_property PACKAGE_PIN P15 [get_ports {a_to_g[4]}]
set_property PACKAGE_PIN T11 [get_ports {a_to_g[5]}]
set_property PACKAGE_PIN L18 [get_ports {a_to_g[6]}]
set_property PACKAGE_PIN J17 [get_ports {an[0]}]
set_property PACKAGE_PIN J18 [get_ports {an[1]}]
set_property PACKAGE_PIN T9 [get_ports {an[2]}]
set_property PACKAGE_PIN J14 [get_ports {an[3]}]
set_property PACKAGE_PIN P14 [get_ports {an[4]}]
set_property PACKAGE_PIN T14 [get_ports {an[5]}]
set_property PACKAGE_PIN K2 [get_ports {an[6]}]
set_property PACKAGE_PIN U13 [get_ports {an[7]}]