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do-you-know-backend
๐ฅ This repository contains contents about overall knowledge of backend
https://bkjang.github.io/do-you-know-backend
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Introduction
#1
Open
BKJang
opened
4 years ago
BKJang
commented
4 years ago
๐ Reference
Operating System Concepts 10th Edition
Thanks to
@jigi-kim
BKJang
commented
4 years ago
Introduction
Computer System์ ์ธ ๊ฐ์ง ๊ณ์ธต์ผ๋ก ๋๋ ์ ์๋ค.
Hardware
System(Operating System) => ํ๋์ Harware์์ ์ฌ๋ฌ ์ ํ๋ฆฌ์ผ์ด์ ์ด ๋ ์ ์๋๋ก ํด์ฃผ๋ ์ญํ (Ease of use to Applications)
Application
System์ด๋ Application์ด๋ ๋ ๋ค Software์ง๋ง ๋๋ ์ ์๋ ์ด์ ๋ ๋ญ๊น?
Military, Government Uses => General(์ผ๋ฐ์ ์ธ) Purpose๋ก ์ ํ
๊ฐ๊ฐ์ ๊ธฐ๋ฅ์ ํ๋ ์ปดํจํฐ๋ค์์ ๊ณตํต์ ์ผ๋ก ํ๋์จ์ด๋ฅผ ์ ์ดํ๋ ๊ธฐ๋ฅ์ ๋ฌถ์ผ๋ฉด์ System์ด ๊ตฌ์ฑ๋๋ค.
Application vs System vs Hardware
Problem Solver vs Execution Environment vs Calculator
User of Resources vs Resource Manager vs Resources
System์ด ํ์ํ ์ด์ ?
Hello World
๋ฅผ ํ ์ค๋ก ์งค ์ ์๋ ์ด์
Application Level์ ์ฌ์ฉํธ์์ฑ๊ณผ ํจ์จ์ฑ์ ์ ๊ณต
Hardware Level์ ๋ณดํธ(๊ฐ๊ฐ์ Application์ด Hardware์ ์ง์ ์ ์ธ ์ํฅ์ ๋ฏธ์น์ง ์๋๋ก) - Protection
JVM, Tomcat๋ ๊ฒฐ๊ตญ Application Level
Hardware
Turing Machine์ Head๋ CPU, ๋ ๋ RAM.
์์ฆ ์ปดํจํฐ๋ ๋๋ถ๋ถ
ํ๋ง ์์ ํ๋ค
.
System Bus
Processor์ I/O์ Main memory๊ฐ์ ์ ๋ณด๋ฅผ ์ ๋ฌํ๊ธฐ ์ํ ๊ท์ฝ
Processor
Central Processing Unit(CPU)
Store data in a set of registers
R0-N
PC(Program Counter): ์์ค์ฝ๋๊ฐ ์ด๋๋ฅผ ์คํํ๊ณ ์๋์ง๋ฅผ ๊ฐ๋ฆฌํด
SP(Stack Pointer): ์คํ์ ๊ฐ๋ฆฌํด
LR(Link Register)
ControlUnit: Head๋ฅผ ์์ง์ด๋ ์ญํ
Store data in a set of registers (Control Unit) => ํ๋์จ์ด๋ฅผ ์ปจํธ๋กคํ๋ ์ญํ
์๋ฅผ ๋ค์ด, ๋ชจ๋ํฐ๋ฅผ ํค๊ธฐ ์ํด ๋ชจ๋ํฐ์ '์ผ์ค!'๋ผ๋ ๋ช ๋ น์ ์ ๋ฌํ๋ ๊ฒ
ALU: Turing Machine์ Head๊ฐ ์ด๋๋ก ์์ง์ผ์ง๋ฅผ ๊ณ์ฐํด์ฃผ๋ ์ญํ
Arithmetic logic circuit (ALU)
์๋ฅผ ๋ค์ด,
int a = 2;
์์
a
์
2
๋ฅผ ํ ๋นํ๋ ๊ฒ
ํ๋์ ๋ ์ง์คํฐ์์ ๋ด์ ์ ์๋ ๋ฐ์ดํฐ๋ 32๋นํธ ์ปดํจํฐ๋ 32๋นํธ 64๋นํธ ์ปดํจํฐ๋ 64๋นํธ(R0-N, PC, SP, LR)
PC(Program Counter): ํ๋ก๊ทธ๋จ์ ์์ฐจ์ ์ผ๋ก ์ํํ๋ ๋ ์ง์คํฐ
SP(Stack Pointer): Stack์์์ ๊ฐ์ฅ ๋ง์ง๋ง์ ๋ค์ด๊ฐ ์์น๋ฅผ ๊ฐ๋ฆฌํจ๋ค.
LR(Link Register): function์ ์ํํ๊ณ ๋์๊ฐ ์์น๋ฅผ ์ ์ฅํด๋์ ๋ ์ง์คํฐ
Read data and instructions from main memory(Control Unit)
ํฐ ๋ ธ์ด๋ง ์ํคํ ์ณ: Data์ Instruction์ ๋ค ๊ฐ์ด ๊ฐ๊ณ ์๋ ๊ตฌ์กฐ(ํ์ฌ ๋๋ถ๋ถ์ ์ปดํจํฐ)
CPU - Memory(Data + Instruction)
ํ๋ฒ๋ ์ํคํ ์ณ: Data์ Instrunction์ ๋ฐ๋ก ๊ฐ๋ ๊ตฌ์กฐ
Memory(Data) - CPU - Memory(Instruction)
Main Memory(RAM, Random Access Memory) - Primary Storage
Volatile(ํ๋ฐ์ฑ)
rewritable(Data์ overwrite)
random-accessible
Array of bits, bytes, kilobytes... and words
word: cpu๊ฐ ๋ฉ๋ชจ๋ฆฌ์์ ํ ๋ฒ์ ์ฝ์ด์ฌ ์ ์๋ ๋จ์
Each byte has its own address
32๋นํธ ์ปดํจํฐ๋ 2^32๋นํธ ๋งํผ์ ์ธ ์ ์๋๋ฐ ์ด๋ 4GB์ด๋ฏ๋ก ๋ฉ๋ชจ๋ฆฌ๋ 4GB๋ง ์ธ ์ ์๋ค.
Processor์ Main Memory
Instruction Cycle
Fetch an instruction from the memory address written in PC.
Decode and execute th instrction then write back.
Update the value written in PC.
Fetch => Decode => Execution
Fetch instruction from the address of memory written in PC.(Automatically)
Decode and execute the instruction
Update the value written in PC to point next address(Automatically)
I/O => Storage - Secondary Storage
Non-volatile, huge compared to Main memory
slower than main memory
rapidly emerging, evolving => HDD / SSD / PRAM
PRAM(Persistent RAM) : RAM + Storage
Storage Device Hierarchy
Small but Fast => Huge but Slow
Register < Cahce < RAM < SSD < HDD < External Storage
Primary
Register
Cache: ํ๋ฒ๋ ์ํคํ ์ณ๋ฅผ ์ฌ์ฉ(์๋๊ฐ ์ต์ฐ์ ์ด๊ธฐ ๋๋ฌธ์ Data Cache์ Instrunction Cache๋ฅผ ๋ถ๋ฆฌ)
RAM
Secondary
SSD
HDD
Tertiary
External Storage
Processor์ I/O
IO
The way users get/put the data, from/to computer.
Mostly, have their own controller.
Device controllers operate independently.
Driver: CPU์ I/O๊ฐ์ ํต์ ํ๊ธฐ ์ํ ๊ท์ฝ์ด ์ ์๋ ๊ฒ.
Interrupts
The way to synchronize I/O devices and CPU
The signal for devices to inform CPU(e.g. finish its job)
CPU must handle interrupts as soon as possible
Life of Interrupts
An I/O device raises an iterrupt by sending signal to CPU(Interrupt Request, IRQ)
Interrupt controller wihin CPU catches th signal
CPU jumps to interrupt vector, dispatch and clear IRQ.(Interrupt Service Routine, ISR)
System Bus
Processor, I/O, Main Memory๊ฐ์ ๋ฐ์ดํฐ๋ฅผ ์ฃผ๊ณ ๋ฐ์ ์ ์๋๋ก ํด์ฃผ๋ ์ญํ
๋ฐ์ดํฐ๋ฅผ ์ด๋ป๊ฒ ์ฃผ๊ณ ๋ฐ์์ง๋ฅผ ์ ํด๋์ ์ธํฐํ์ด์ค
How can we print out "Hello World" with single line?
CPU moves program from storage to main memory.
CPU commands a serial device to print out a chracter.
Serial Device๋ ๋ฌธ์๋ฅผ ์ถ๋ ฅํ๊ณ ๊ทธ ๋ค์ ๋ฌธ์๋ฅผ CPU์๊ฒ ์์ฒญ.
DMA(Dynamic Memory Access)
DMA๋ I/O๊ธฐ ๋๋ฌธ์ Interrupt๊ฐ ๋ฐ์ํ๋ค.
์ ์ผํ๊ฒ ๋ฉ๋ชจ๋ฆฌ์ ์ง์ ์ ๊ทผ ๊ฐ๋ฅํ ์์ด
์์ 2~3์ ๊ณผ์ ์์ overhead๊ฐ ์ผ์ด๋ ์ ์๋๋ฐ DMA๋ฅผ ํตํด CPU์๊ฒ ๋งค๋ฒ ๊ฐ๋ Interrupt๋ฅผ DMA์์ ์ํํ๋ค.
Single-Processor System
Core : Execute instruction and stroe data locally
With other components to support the core
Processor became bottleneck
Multi-Processor System
Multiple processors with single core for each
AMP(Asymmetric Multi Processing)
๊ฐ๊ฐ์ ํ๋ก์ธ์๋ ๋ค๋ฅธ ์ญํ
SMP(Symmetric Multi Processing)
๊ฐ๊ฐ์ ํ๋ก์ธ์๊ฐ ๋ชจ๋ ์ญํ ์ ๋ถ์ฐ
์ผ๋ฐ์ ์ผ๋ก SMP๋ฐฉ์์ ์ฑํ
To increase throughput N times
However, the throughput actually is "<=N" times
Multi-Core System
Multiple cores within single processor
Fast communication and low power consumption(๋ฉํฐ ํ๋ก์ธ์ ์์คํ ์ ์์คํ ๋ฒ์ค๋ฅผ ํตํด ํต์ ํ์ง๋ง ๋ฉํฐ ์ฝ์ด ์์คํ ์ ๋ด๋ถ์ ์ผ๋ก ์ผ์ด๋๊ธฐ ๋๋ฌธ์ ์๋์ ์ผ๋ก ์ฑ๋ฅ์ด ๋ ์ข๋ค)
Still have some problem, but currently standard
NUMA(Non-Uniform Memory Access)
Multiple processors with local memory for each (ํ๋ก์ธ์๋ณ๋ก ๋ฉ๋ชจ๋ฆฌ๊ฐ ๋ค ๋ฐ๋ก ์กด์ฌ)
์ฝ์ด๋ ์ฌ๋ฌ ๊ฐ์ง๋ง ๋ฉ๋ชจ๋ฆฌ๋ ํ๋๋ค๋ณด๋ ๋ชจ๋ ์ฝ์ด์์ ํ๋์ ๋ฉ๋ชจ๋ฆฌ์ ์ ๊ทผํ๊ฒ ๋๋ค. ๊ทธ๋ฌ๋ค๋ณด๋ ์์คํ ๋ฒ์ค์ ๋ณ๋ชฉํ์์ด ์ผ์ด๋๋ค.
Latency on remote access <= This is hot
Memory๊ฐ์ ๋์์ฑ ์ฒ๋ฆฌ๋ Core ๊ฐ์ ํต์ ์ผ๋ก ํด๊ฒฐ
๋ฌผ๋ฆฌ์ ์ผ๋ก Memory๊ฐ ์ฌ๋ฌ ๊ฐ
Clustered System
Multiple Computers with single storage
Asymmetric Clustering
ํ๋์ ์ปดํจํฐ๊ฐ ์ฃฝ๋๋ค๋ฉด ๋ชจ๋ํฐ๋ง๋ง ํ๋ ์ปดํจํฐ๊ฐ ๊ทธ ์ญํ ์ ์ํ
Symmetric Clustering
๋ชจ๋ ์ปดํจํฐ๊ฐ ๋ชจ๋ํฐ๋ง์ ์งํํ๊ณ ๊ฐ์ฅ ์ฌ์ ์๋ ์ปดํจํฐ๊ฐ ์ฃฝ์ ์ปดํจํฐ์ ์ญํ ์ ์ํ
High availability service
Need to reprogram application for parallelization
Today's Computer System
Personal Computing
Embedded mobile computing
Client-server computing
Peer to peer computing
Cloud Computing
Real-time embedded computing
System
Life of Operating System (Boot Sequence)
์ต์ 1๊ฐ์ ๋ฉ๋ชจ๋ฆฌ์ 1๊ฐ์ Core
Boot Loader๋ฅผ ํตํด Memory์ OS๊ฐ ์ฌ๋ผ๊ฐ
Initialize primary CPU and other components in processor
Set up system components to operates computer
Wake secondary CPUs and initialize devices (ex. DMA ์ด๊ธฐํ)
Execute system programs(daemon) and become idle
OS Waiting for any events to occur
Execution of Application Software
Program initially is stored in storage device
Load progream into main memory
Execute code of program line by line
Process
Active instance of program in execution
Use computer resources to perform its tasks
What if process becomes idle?
Multiprogramming
ํ๋์ ํ๋ก์ธ์ค๊ฐ ๋๊ณ ์๋ ๋์์๋ ๋ค๋ฅธ ํ๋ก์ธ์ค๋ฅผ ์คํ
Keep users stisfied and reduce CPU idle time
Need techniques for resources to be shared
Multitasking
์ฌ๋ฌ ๊ฐ์ ํ๋ก์ธ์ค๋ฅผ ๋๊ณ ๋์ํ๊ณ ๋ฅผ ๋ฐ๋ณต
์๋ถํ ์ด์์ฒด์
Switch processes periodically and frequently
Provide faster response time to users
Use timer to maintain control over CPUs
timer
Use clock signal and tick counter to get percise time
Periodic - Generate interrupts on every N times
One shot - Generate interrupts after N ticks
Multimode Operation
Hardware support for various execution modes
At least two level - Kernel mode & user mode
Limit every hardware access and some instructions
mode bit๋ฅผ ํตํด User Mode์ Kernel Mode๋ฅผ ๋ฐ๋ก ๊ด๋ฆฌ
Scenario of Multimode Operation
OS booting scene: Kernel Mode
After booting: User Mode
Any events given to Kernel: Kernel Mode
User Mode => Kernel Mode๋ก ์ค๋ ๊ฒฝ์ฐ๋ฅผ Exception(Trap)
Unauthorized hardware access from application
Interrupts raised by any hardware devices
Service requests from application to kernel
๊ฒฐ๊ตญ System Call(Software Interrupt, SWI)๋ Exception์ ํตํด์ ์ผ์ด๋๋ ๊ฒ
Kernal Mode์ User Mode๊ฐ ์๋ก ๋์ด๊ฐ ๋ Context Switching์ด ์ผ์ด๋๋ค.
Today's Operating System(POSIX Standard๋ฅผ ํตํด ๊ฐ๋ฐ)
Multics(1964 / MIT, AT&T, GE)
UNIX(1969 / Dennis Ritchie) - With C Language
BSD(1977 / CSRG @ UC Berkeley)
LINUX(1991 / Linus Trovalds) - And ... Git in 2005
Darwin(2000 / Apple)
Windows NT(1993 / Microsoft)
๐ Reference