how to run synthesis and implementation of this design targeting a specific Xilinx FPGA board ?

BLu85 / AES-GCM-128-192-256-bits

Configurable AES-GCM IP (128, 192, 256 bits)

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how to run synthesis and implementation of this design targeting a specific Xilinx FPGA board ? #11

Closed lizajoseph closed 1 month ago

lizajoseph commented 1 month ago

I tried to target this design on a Alveo u50 card by adding all the .vhd files and the .sdc file. There is no .xdc file available in the design package. The vivado runs fail at implementation due to IO placement issues and instances not placed.

It will be helpful to have the steps to run synthesis, implementation and generate the bit file and validate the bitfile on the FPGA card.

BLu85 commented 1 month ago

Hi @lizajoseph,

This is an IP project. It can be instantiated inside any FPGA or ASIC design. You would probably want to open this issue on a Xilinix forum to get help on your specific problem.

Luca