Key expansion not working correctly on Vivado

[weedeagle]

I tried to run the entire code on Vivado but it threw out output just the same as the input. I checked and it seemed like the aes_kexp block was not working correctly, output kexp_key_next_part_o[7:4] and kexp_key_last_stage_o were equal to X when kexp_dval_i asserted.

[BLu85]

Hi @weedeagle,

thanks for reporting this. Could you give more details about your AES configuration? What command did you run to create the .vhd files?

Thanks.

[BLu85]

I might think that the issue is in the aes_kexp.vhd file. When the IP is configured for keys of 128 and 192 bits, the flops in some vectors that form the signal kexp_key_next_part_o are not driven, hence are floating, when the reset is released. This is the part I am talking about:

    sample_key_p: process(rst_i, clk_i)
    begin
        if(rst_i = '1') then
            w_0_q   <= RST_WORD_C;
            w_1_q   <= RST_WORD_C;
            w_2_q   <= RST_WORD_C;
            w_3_q   <= RST_WORD_C;
            w_4_q   <= RST_WORD_C;
            w_5_q   <= RST_WORD_C;
            w_6_q   <= RST_WORD_C;
            w_7_q   <= RST_WORD_C;
        elsif(rising_edge(clk_i)) then
            if(kexp_dval_i = '1') then
                if(aes_mode_i = AES_MODE_128_C) then

As you can see w_0_q is not defined when the reset is released, so in theory those are flops with floating inputs. The tool should be cleaver enough to sythesise those flops away during the synthesis process. To avoid the X you are seeing, we could add the missing w_x_q signals inside the if statements and connect them to their reset value RST_WORD_C.

For example:

    sample_key_p: process(rst_i, clk_i)
    begin
        if(rst_i = '1') then
            w_0_q   <= RST_WORD_C;
            ...
            w_7_q   <= RST_WORD_C;
        elsif(rising_edge(clk_i)) then
            if(kexp_dval_i = '1') then
                if(aes_mode_i = AES_MODE_128_C) then
                    w_7_q <= w_0;
                    ...
                    w_0_q <= RST_WORD_C;
                elsif(aes_mode_i = AES_MODE_192_C) then
                    w_7_q <= w_in_3;
                    ...
                    w_0_q <= RST_WORD_C;
                else
                    ...
                end if;
            end if;
        end if;
    end process;

[BLu85]

I added the fix in version 1.8. Please, let me know if this is now solved for you.

Thanks, Luca

[weedeagle]

Hi Luca, The problem is resolved. Huge thanks for your support.

[BLu85]

Marvellous, I'll close the issue. Thanks.