BMellor EmbLab issues - Githubissues

BMellor / EmbLab

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Mention the TIM_CCER register in lab 3

#21 BMellor opened 7 years ago
0
Mention the SYSCFG EXTICRx array

#20 BMellor opened 7 years ago
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ST released new version of reference manual

#19 BMellor opened 7 years ago
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EXTI peripheral doesn't require enable in RCC

#18 BMellor closed 7 years ago
1
Redo figures in lab

#17 BMellor opened 7 years ago
0
Required reset of discovery board

#16 BMellor opened 7 years ago
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Add delay to debounce code example

#15 BMellor opened 7 years ago
0
Confusing BSSR register in first lab

#14 BMellor opened 7 years ago
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Wrong part in lab manual (disco board has larger variant)

#13 BMellor opened 7 years ago
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3.5.2: May want to reference the IRQ Handler here

#12 alexferro opened 7 years ago
0
WFI/WFE sleep modes

#11 alexferro opened 7 years ago
0
3.3.3: "Unlike systems having only hardware interrupt priorities, "

#10 alexferro opened 7 years ago
3
3.3.2: Tail-chaining applies to lower priority as well.

#9 alexferro opened 7 years ago
0
3.3.2: “Depending on these priories there are two” priorities

#8 alexferro closed 7 years ago
1
3.3.1 IPR

#7 alexferro opened 7 years ago
0
3.3.1: “STM32F0s”

#6 alexferro opened 7 years ago
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3.3.1: core_cm0.h

#5 alexferro opened 7 years ago
1
3.2: RESET vector table instructions?

#4 alexferro opened 7 years ago
0
3.2: Is RESET really an interrupt?

#3 alexferro opened 7 years ago
0
Link to logic analyzer chapter when complete

#2 BMellor opened 7 years ago
0
Explain ARM-core interrupts and their negative priorities.

#1 BMellor opened 7 years ago
0