Closed Jerryy959 closed 3 months ago
From now on, I will use extensive length to describe and track this issue.✅ Just start.🚀
We can find the source code here.
val pmaPgLevelHomogeneous = (0 until pgLevels) map { i =>
val pgSize = BigInt(1) << (pgIdxBits + ((pgLevels - 1 - i) * pgLevelBits))
if (pageGranularityPMPs && i == pgLevels - 1) {
require(TLBPageLookup.homogeneous(edge.manager.managers, pgSize), s"All memory regions must be $pgSize-byte aligned")
true.B
} else {
TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), pgSize)(r_pte.ppn << pgIdxBits).homogeneous
}
}
Tips:
Where pgLevels
represents the number of levels in page table translation, we used 2
, due to:
Just take a look for line 12.
require
is an assertion, if true, return (true.B), else raise error.
The most crucial statement is in:
TLBPageLookup.homogeneous(edge.manager.managers, pgSize)
Function defined here:
This homogeneous method is used to check whether all memory areas in managers meet a condition, that is, whether their alignment values are greater than or equal to the specified pageSize. In other words, it ensures that all mapping areas are aligned on the given pageSize, thus ensuring homogeneity.
Chatgpt: 一致的对齐方式要求所有内存区域的起始地址都在某个固定大小(如 pageSize)的倍数上。这样可以保证内存访问的效率,并避免潜在的性能问题或硬件错误。
Let’s summarize.
Check this commit, add some debug code, https://github.com/BOSC-Hvisor/rocket-chip/commit/3966df00e24499127734ca05b8f27b38a58a371c
i get the follow output:
Region AddressSet(0x3000000, 0x3ff) is not aligned to pageSize 4096.
Not all regions are homogeneous with pageSize 4096.
which means the region (0x3000000, 0x3ff) would cause error.
This AddressSet describes the address range from 0x300 0000 to 0x300 03ff.
Next, maybe we should take a look at the device tree?
fine, i found that 0x3000000 corresponds to this device in the device tree, which is exactly the new field added by the original author. Perhaps we should consider removing it.
make -C ./rocket-chip/emulator/ PROJECT=freechips.rocketchip.uintr CONFIG=freechips.rocketchip.uintr.UintrConfig MODEL=Top verilog
check this command.
We can see that dts has already integrate the soc.
Found a new problem: which part is my zcu102 belongs?
3.4 or 3.3?
❗️Should i create a new issue to figure out this?
it works fine.🇨🇳
The specific English command is:
I suggest to open a new issue to resolve this.
Originally posted by @Jerryy959 in https://github.com/BOSC-Hvisor/hvisor-rocket-chip/issues/2#issuecomment-2299697070