Vector size can not be parametrized by module parameter

[m1a1x1]

I have a trouble with understanding some BSC compiler error. I do not know is this is a right place to ask about code/language issues and if it is not, I am really sorry. I have already registered on http://forum.bluespec.com but my account is not active yet.

I have a small minimal design, where I can found my problem:

package Test;
import Vector      :: *;
(* synthesize *)
module mkQueue #(
  parameter UInt#(32) qsize
) (Empty);
  Vector#(qsize,Reg#(Bit#(8))) queue <- replicateM (mkReg (0));
endmodule
endpackage

Compiling this module with bsc I get next error message:

Verilog generation
bsc -verilog -remove-dollar Test.bsv
Error: "Test.bsv", line 9, column 11: (T0008)
  Unbound type variable `qsize'

bsc version:

Bluespec Compiler (build e55aa23)

And I can not understand, why qsize is Unbound as it is clearly declared as a parameter? If I did something wrong, could you please help me and explain, how to make parameterized size Vector correctly?

Thank you very much in advance. If this is not a right place to ask such questions -- could you please give me a link to the place, where someone can help me.

[rsnikhil]

Dear Maksim,

In future, you can also ask questions at 'support@bluespec.com'.

Please see the attached tar file.

README.txt has an anaysis of your code, and suggestions on how to fix it. I have also expanded the code into a full working example, in the tar file, which you can try building and running.

Best regards, Nikhil for_Maksim.tar.gz

[m1a1x1]

Hello Nikhil, Thank you very much for your help! Now I get it. I really appreciate your fast reply and explanation in README.txt, it is very helpful.

I have asked this question also on StackOverflow: https://stackoverflow.com/questions/60636401/vector-of-registers-size-can-not-be-parametrized-by-module-parameter

But a little latter, than I have asked it here, so there there is one new aspect, that is still not very clear for me: Why this code is legal:

package Test;
import Vector      :: *;
(* synthesize *)
module mkTest #(
  parameter UInt#(32) qsize
) (Empty);
  Vector#(qsize,Bit#(8)) queue = replicate(0);
endmodule
endpackage

The only difference -- type of Vector elements, but for somehow now UInt parameter, not type parameter is legal as Vector size.

I will add link to this issue as a answer to my question on StackOverflow.

[nanavati]

The short version is that this is a limitation on the kinds of Verilog the Bluespec compiler can generate.

A numeric value parameter isn't a problem because the compiler can treat it like an opaque value (similar to the contents of a register) or pass it to underlying Verilog primitives. If you use it in ways where the compiler can't handle it (like instantiating different numbers of registers) you'll get a more specific error message about that.

A numeric type is different because most of the ways you can use it are things the compiler can't handle. There are a few cases (like handling data values of different widths) that the compiler could handle, but those are tricky to implement so they haven't been done yet.

[m1a1x1]

Thank you for you answer, now I get it.