YAML file created using build_vhdl_packages.py for BRAM interfaces

[prisundind]

Hi Andrew, I am trying to use the yaml file created using build_vhdl_packages.py along with the yml2hdl utility to create SystemVerilog header files

It looks like the yaml file that is generated does not have definitions for memory interface. For example in MEM_TEST: there is no definition of “ type: MEM_TEST_MEM1_MOSI_t “ https://github.com/BU-Tools/uHAL_AXI_regmap/blob/047891c3b524ecaa2d3844299f13471890fc5cca/tester/CParserTest_wishbone/MEM_TEST_PKG.yml#L61

Would you be able to add this to regmap?

Best, Priya

[andrewpeck]

Can you try checking out this branch and see if it works for you?

https://github.com/BU-Tools/uHAL_AXI_regmap/tree/fix-memory-yaml-package

[andrewpeck]

It adds e.g.

- MEM_TEST_MEM1_MOSI_t:
 - clk       : [ type: logic ]
 - enable    : [ type: logic ]
 - wr_enable : [ type: logic ]
 - address   : [ type: logic, length: 8 ]
 - wr_data   : [ type: logic, length: 13 ]

- MEM_TEST_MEM1_MISO_t:
  - rd_data       : [ type: logic, length: 13 ]
  - rd_data_valid : [ type: logic ]

[prisundind]

Hi Andrew, Thanks for the quick fix! yml2hdl gives a parserError - one extra space required for all members in *_MOSI_t

You can look at the XML file I am using here - https://gitlab.cern.ch/atlas-tdaq-phase2-l0mdt-electronics/l0mdt-hdl-design/-/blob/PS/FM/address_tables/modules/FM.xml

• FM_SB0_SB_MEM_MOSI_t:
  • clk : [ type: logic ]
  • enable : [ type: logic ]
  • wr_enable : [ type: logic ]
  • address : [ type: logic, length: 8 ]
  • wr_data : [ type: logic, length: 13 ]

[andrewpeck]

Okay, thanks for checking! should be fixed now if you pull the last commit

whitespace sensitive languages uhhg :)

[prisundind]

Hi @andrewpeck , I am getting a syntax error with FM_map.vhd, there is a ";" being printed Ctrl. I fixed this locally by replacing ; with
Mon : in FM_Mon_t;

generic (
    READ_TIMEOUT     : integer := 2048
    );
  port (
    clk_axi          : in  std_logic;
    reset_axi_n      : in  std_logic;
    slave_readMOSI   : in  AXIReadMOSI;
    slave_readMISO   : out AXIReadMISO  := DefaultAXIReadMISO;
    slave_writeMOSI  : in  AXIWriteMOSI;
    slave_writeMISO  : out AXIWriteMISO := DefaultAXIWriteMISO;
    ;
    Ctrl             : out FM_Ctrl_t

    );

[andrewpeck]

Hi Priya, it looks like this happens when you have only a Ctrl but not a Mon record (i.e. write-only)

I think it is fixed in the last commit that I just pushed

it now comes out as:

    slave_writeMISO  : out AXIWriteMISO := DefaultAXIWriteMISO;

    Ctrl             : out FM_Ctrl_t

    );

[andrewpeck]

Can you check if this fixes your issue? If so I will merge this.

[andrewpeck]

Ooh.. wait.. sorry. I misunderstood. It's not just a dangling ; but rather if the slave only has a memory and (maybe) write only registers the script does not detect it as a read/write module.

I can fix this, but I think there may be an issue in the address table you are using:

I think a lot of these or all of these should be rw registers instead of w

w means they are "action registers" or pulsed registers that go high for one and only one clock cycle (e.g. for a reset or write enable etc)

If you want to be able to set something that stays at a value, e.g. a mode, then it should be rw.

  <node id="SPY_CTRL"  address="0x0">
    <node id="GLOBAL_FREEZE" address = "0x0" permission="w" mask="0x1"/>
    <node id="GLOBAL_PLAYBACK_MODE" address="0x0" permission="w" mask="0x6"/>
  </node>
  <node id="FREEZE_MASK_0" address="0x1" permission="w" mask="0xFFFFFFFF"/>
  <node id="FREEZE_MASK_1" address="0x2" permission="w" mask="0xFFFFFFFF"/>
  <node id="PLAYBACK_MASK_0" address="0x5" permission="w" mask="0xFFFFFFFF"/>
  <node id="PLAYBACK_MASK_1" address="0x6" permission="w" mask="0xFFFFFFFF"/>

[andrewpeck]

Okay I think it now correctly puts out:

  port (
    clk_axi          : in  std_logic;
    reset_axi_n      : in  std_logic;

    slave_readMOSI   : in  AXIReadMOSI;
    slave_readMISO   : out AXIReadMISO  := DefaultAXIReadMISO;
    slave_writeMOSI  : in  AXIWriteMOSI;
    slave_writeMISO  : out AXIWriteMISO := DefaultAXIWriteMISO;

    Mon              : in  FM_Mon_t;
    Ctrl             : out FM_Ctrl_t

    );

[prisundind]

Hi @andrewpeck , I verified this fix. Thanks! Please merge to devel

Best, Priya