feature request: Address table packer

[dgastler]

This would be an abstraction layer that would take uHAL or uHAL-like address tables and densely pack registers to minimize the FPGA resources needed to decode the address lookups.

Fully expressed uHAL address tables would pass through intact, but a register with the address of "auto" would have its address assigned by the software.

This would output a new, fully uHAL compatible, flat address table to be used by software for register access.

An additional suggested feature would be to force a new register at relative address 0 in the endpoint to be some kind of hash of the address table so that one can verify the FW and SW match.

[dgastler]

Rules for register merging.

• Merging can only happen within the same address table node level.
• merging must keep read-only, write-only, and read+write registers in separate 32-bit words (should it break up existing mixing of read-only and read+write regs?)
• registers can not be split up across 32bit word boundaries.
• AXI Lite has some options to only update specific sub-bytes of a 32bit-word. Is it worth exploring if we can use this to skip RMWs?
• others? @andrewpeck @eshazen

[dgastler]

Nodes will keep their FW_INFO tags and FW_INFO based arrays must be compressed in the same way.

[dgastler]

Rule #2 should be modified to allow read-only and read+write registers to exist in the same register. Write only registers are only allowed to be mixed with other write-only registers.