Issue with VHDL code generated using memory template (templates/axi_generic/template_map_withbram.vhd)

[prisundind]

In XML file, if registers are not defined in contiguous locations in address range then autogenerated VHDL code does not generate ACK signal for all register reads in valid address range

For example, following XML definition does not have registers at address 0x2, 0x3. But these locations are within register address space.

**MISSING REGISTER DEFINITION for address 0x2, 0x3** ============================= When running dump_debug from BUTools for these nodes, the reads seem to timeout as it does not receive an ACK. When running with template_map_withbram.vhd - For each node, would it be possible to define boundaries for register mapping and respond with regRdAck (even if register not defined in XML). The read data can be encoded to indicate that register address is not defined in XML ======================================== case to_integer(unsigned(localAddress(9 downto 0))) is ---> **THIS SHOULD EXCLUDE BRAM MEMORY ADDRESS SPACE** when 16 => --0x10 localRdData( 0) <= Mon.MGT.MGT(0).STATUS.rxcdr_stable; -- localRdData( 1) <= Mon.MGT.MGT(0).STATUS.powergood; -- localRdData( 2) <= Mon.MGT.MGT(0).STATUS.txready; -- . . . . when others => regRdAck <= '1'; localRdData <= x"deadbeef"; --> **RETURN A CODE THAT WOULD FLAG THAT REGISTER IS UNDEFINED IN ADDRESS SPACE** end case; ===============

[dgastler]

What are you trying to do? Read a range based only on the uhal address, not the name?

[dgastler]

If you did this I think it would break the BRAM reads.

[prisundind]

This issue happens if address mapping in XML file contain nodes with implied address but no permissions on it. The workaround for this would be to explicitly specify permissions for all nodes in XML file.