CVTTSS2SI use wrong operand types

[Kashio]

Right now CVTTSS2SI encoded with opcode F3 0F 2C use operand type ss for its operand of addressing W which is defined as:

Scalar element of a 128-bit packed single-precision floating data.

According to the intel docs:

Converts a single-precision floating-point value in the source operand (the second operand) to a signed doubleword integer (or signed quadword integer if operand size is 64 bits) in the destination operand (the first operand). The source operand can be an XMM register or a 32-bit memory location. The destination operand is a general purpose register. When the source operand is an XMM register, the single-precision floating-point value is contained in the low doubleword of the register.

Since it's only copying the lower 32 bits of the register and the memory variant is also referencing 32 bit memory the operand type should be of type d which is defined as:

Doubleword, regardless of operand-size attribute.

[BarebitOpenSource]

This one looks right. Refer to #23.

[BarebitOpenSource]

Feel free to reopen this issue if you still think the operand type is wrong.