Right now SQRTSS encoded with opcode F3 0F 51 use operand type ss for its operand of addressing W which is defined as:
Scalar element of a 128-bit packed single-precision floating data.
According to the intel docs:
Computes the square root of the low single-precision floating-point value in the second source operand and stores the single-precision floating-point result in the destination operand. The second source operand can be an XMM register or a 32-bit memory location. The first source and destination operands is an XMM register.
Since it's only operate on the lower 32 bits of the register and the memory variant is also referencing 32 bit memory the operand type should be of type d which is defined as:
Right now
SQRTSS
encoded with opcodeF3 0F 51
use operand typess
for its operand of addressingW
which is defined as:According to the intel docs:
Since it's only operate on the lower 32 bits of the register and the memory variant is also referencing 32 bit memory the operand type should be of type
d
which is defined as: