Open leoqiao18 opened 11 months ago
Ya I think we'll need to look at the sygus logs to figure out what queries are being made, and why we aren't getting the right assumptions added
Looks like we need to try to schedule a call with @wonhyukchoi to fix this issue
We need
and it seems we don't have support for this in the new implementation of TSL-MT (I am pretty sure it was there in the old implementation that @wonhyukchoi made for the PLDI paper though)
Also, I'm actually thinking, at least as a hack for now, just brute force generating all the assumptions of this particular form. Would be fairly easy and this is the most common equality+temporal form we need
An issue in a spec that came from @w14 :
This should be realizable by always assigning 0 to y. But
tsl synthesize
fails at the ltlsynt step.The problem comes from a lack of assumptions generated by the ModuloTheories step. Running
tsl theorize
gives the following theorized spec:Notice that the ModuloTheories step only adds a bunch of repeated points about how y cannot be equal to 0 and not be equal to 0 at the same time. It did not add anything about how assigning 0 to y causes y to be equal to 0 in the next time step.
This might be related to the issue that @santolucito talked about in #64