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BatchDrake / SigDigger

Qt-based digital signal analyzer, using Suscan core and Sigutils DSP library
https://batchdrake.github.io/SigDigger/
GNU General Public License v3.0
954 stars 93 forks source link

how to interface custom fpga data stream to SigDigger #202

Open hoarylea opened 1 year ago

hoarylea commented 1 year ago

Mr. BatchDrake I am a hardware engineer, focus on fpga development. could you please guide me on how to interface fpga stream to SigDigger. thanks.

BatchDrake commented 1 year ago

Hi,

SigDigger relies on SoapySDR for device interfacing, and uses it to read I/Q samples from them in a sort-of agnostic way. It boils down to writing the corresponding SoapySDR module, and make sure SigDigger is able to recognize it (which should not be difficult).

This, or course, is in case you are intending to use your FPGA to deliver a stream of I/Q samples to SigDigger. If you had something else in mind, we may need to look for alternatives.

Cheers,

El lun., 3 abr. 2023 15:45, hoarylea @.***> escribió:

Mr. BatchDrake I am a hardware engineer, focus on fpga development. could you please guide me on how to interface fpga stream to SigDigger. thanks.

— Reply to this email directly, view it on GitHub https://github.com/BatchDrake/SigDigger/issues/202, or unsubscribe https://github.com/notifications/unsubscribe-auth/AAEVET42RWYTQUR6BOEJJY3W7LH6HANCNFSM6AAAAAAWRLDHYY . You are receiving this because you are subscribed to this thread.Message ID: @.***>

BatchDrake commented 1 year ago

Hi @hoarylea

Is there anything else I can help you with?

Cheers,