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Change C28, C29 to 1uF #4

Closed transmogrifox closed 7 years ago

transmogrifox commented 7 years ago

Changing ADC level changes input impedance to a value as low as 20 k ohms. With 0.1 uF value as shown in the BOM, the high-pass cut-off is:

1/(2*pi*20k*0.1u) = 79.6 Hz
|h|dB = 20*log10[ sqrt((s*r*c)^2)/sqrt(1+(s*r*c)^2) ]
|h|dB = -12.2612

A change to 1 uF will have the following effect:

s = j2*pi*20
r = 20k
c = 1u

fc=1/(2*pi*r*c)
fc = 7.9577

|h|dB = 20*log10[ sqrt((s*r*c)^2)/sqrt(1+(s*r*c)^2) ]
|h|dB = -638.2644m

The proposed DSP high-pass (DC removal) filter is also designed for 8 Hz cut-off, which yields another -638 mdB for a combined response of -1.28 dB at 20 Hz and -55mdB at 100 Hz (99%).

TLV320AIC3104 datasheet page 36:

In most cases, the analog input pins on the TLV320AIC3104 should be ac-coupled to analog input sources, the exception to this being if an ADC is being used for dc voltage measurement. The ac-coupling capacitor causes a high-pass filter pole to be inserted into the analog signal path, so the size of the capacitor must be chosen to move that filter pole sufficiently low in frequency to cause minimal effect on the processed analog signal. The input impedance of the analog inputs when selected for connection to an ADC PGA varies with the setting of the input level control, starting at approximately 20 kΩ with an input level control setting of 0 dB, and increasing to approximately 80 kΩ when the input level control is set at –12 dB. For example, using a 0.1-μF ac-coupling capacitor at an analog input results in a high-pass filter pole of 80 Hz when the 0-dB input level control setting is selected