Add PHX/PLX and PHY/PLY - Githubissues

BigEd / verilog-6502

This fork family includes the 6502 upgraded to 32-bit address bus, in Verilog HDL

https://github.com/BigEd/verilog-6502/wiki

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Add PHX/PLX and PHY/PLY #3

Open BigEd opened 13 years ago

BigEd commented 13 years ago

These are quite difficult to replace with macros and very useful to preserve registers.

They are defined in 65C02

BigEd commented 12 years ago

Arlet implementation notes from http://forum.6502.org/viewtopic.php?p=15834#p15834:

In the first place, the opcode mask needs to include the new opcode here http://github.com/Arlet/verilog-6502/blob/c51aa17b6b1a4de23184815fd404b4670186f8ae/cpu.v#L877

Secondly, it needs an extra opcode mask to set src_reg to SEL_X register here https://github.com/Arlet/verilog-6502/blob/c51aa17b6b1a4de23184815fd404b4670186f8ae/cpu.v#L1016

Of course, with all opcode extensions you have to watch out that the new opcode doesn't overlap with a "don't care" in one of the existing patterns.