Teensy 4.0- Memory tests fail with reads offset by 1 byte?

[dirkenstein]

I added an ISSI 2-die 4mbit flash chip to my TGA board and am getting very weird failures when running BALibrary DMA tests (see below)

Either the write or the read back is off by 1 byte- not sure which way it is but it looks to be the read.

This is using DMA_MEM0_test.ino

You can get the 8-bit tests to pass by increasing size of dest buffer by 8, reading DMA_MEM + 4 bytes and then doing the compare at dest+1.

Enabling SPI, testing MEM0

Starting 8-bit test Write/Read 0:: a:170 does not match b:0 1:: a:171 does not match b:170 2:: a:168 does not match b:171 3:: a:169 does not match b:168 4:: a:174 does not match b:169 5:: a:175 does not match b:174 6:: a:172 does not match b:175 7:: a:173 does not match b:172 8:: a:162 does not match b:173 9:: a:163 does not match b:162 ERROR @0

Starting 16-bit test 0:: a:170 does not match b:0 2:: a:171 does not match b:170 3:: a:170 does not match b:171 4:: a:168 does not match b:170 5:: a:170 does not match b:168 6:: a:169 does not match b:170 7:: a:170 does not match b:169 8:: a:174 does not match b:170 9:: a:170 does not match b:174 10:: a:175 does not match b:170 ERROR @0

TEST DONE!

[Blackaddr]

You are correct, it will be off by one byte. The ISSI die does not use actual SRAM, it uses DRAM with a small built-in DRAM controller otherwise known as Psuedo-SRAM (PSRAM). As a result of this, it has an extra cycle of latency that is not present in normal SPI SRAM. This is documented in the chips datasheet. You can compare it to the datasheet of the standard supported SRAM chip 23LC1024 and compare the read timing diagrams.

The easiest way to use these PSRAM chips is to see if you can put it in a legacy compatibility mode that does not have the extra read latency cycle in order to behave like traditional SPI SRAM. I've often seen these chips support this as long as you stick to lower frequencies.

The memory support in the BALibrary uses the standard SPI SRAM protocol. You would need to modify it to support the extra latency from these non-standard PSRAM chips.

Let me know if you get your ISSI PSRAM working in a legacy mode.

[dirkenstein]

Sorry, I checked the datasheet for the IS62WVS5128GBLL and there doesn't seem to be legacy mode unless you activate it using the reserved bits in the mode register (undocumented).

I think I'm going to have to add dummy read cycles to make this work. Not sure how to go about it in DMA mode- without double buffering anyway.

[dirkenstein]

Added dummy reads- works even in DMA mode when i use: dummy = m_spi->transfer(0);

[Blackaddr]

I'm glad you got it working!