castigli
commented
3 years ago Cases
Kernels
Using the mod file example from above, I looked at 4 different kernels:
- simple
- exp
- gather
- ode
llvm vector size
For the first kernel, I looked at the following llvm vector size:
- 8
- 16
- 32
micro architectures
As in the example I looked at the following micro architectures:
- nehalem
- haswell
- skylake The assembly generated is virtually identical (except for vector instructions and unrolling levels).
Observations
For reference this is the data struct with offsets in bytes
INSTANCE_STRUCT {
DOUBLE *minf : 0
DOUBLE *mtau : 8
DOUBLE *m :16
DOUBLE *Dm :24
DOUBLE *v_unused :32
DOUBLE *g_unused :40
DOUBLE *voltage :48
INTEGER *node_index :56
DOUBLE t :64
DOUBLE dt :72
DOUBLE celsius :80
INTEGER secondorder :88
INTEGER node_count :92
}simple
- there are some ops that could be removed from the loop
- register pressure is low, so not sure why more registers are not used
- some instructions can be removed if loop var is made size_t
- loop unrolling is n = sizeof(llvm_vec)/sizeof(target_vec)
vec x 8
nrn_state_hh: # @nrn_state_hh # %bb.0: movl 92(%rdi), %ecx # mech->nodecount leal -7(%rcx), %eax # mech->nodecount - 7 testl %eax, %eax # mech->nodecount - 7 <= 0? jle .LBB0_1 # %bb.6: # %for.body.preheader xorl %eax, %eax # eax will be id, set counter to zero .p2align 4, 0x90 .LBB0_7: # %for.body # =>This Inner Loop Header: Depth=1 cltq # sign extend eax -> rax (this instruction could be avoid with size_t loop var) movq (%rdi), %rcx # mech->minf to rcx | (these 3 ops could be outside the loop) movq 8(%rdi), %rdx # mech->mtau to rdx | movq 16(%rdi), %rsi # mech->m to rsi | vmovapd (%rcx,%rax,8), %zmm0 # load packed double mech->minf[id] to zmm0 vsubpd (%rsi,%rax,8), %zmm0, %zmm0 # mech->minf[id] - load pd mech->m[id] vdivpd (%rdx,%rax,8), %zmm0, %zmm0 # (mech->minf[id] - mech->m[id]) / load pd mech->mtau[id] vmovapd %zmm0, (%rsi,%rax,8) # store packed double to mech->m[id] addl $8, %eax # increment id movl 92(%rdi), %ecx # mech->nodecount | (these 2 ops could be outside the loop) leal -7(%rcx), %edx # mech->nodecount - 7 | cmpl %edx, %eax # id < mech->nodecount -7? jl .LBB0_7 # ...scalar loop...
vec x 16
# ...only vec loop body...
.LBB0_7: # %for.body
# =>This Inner Loop Header: Depth=1
cltq
movq (%rdi), %rcx
movq 8(%rdi), %rdx
movq 16(%rdi), %rsi
vmovapd (%rcx,%rax,8), %zmm0
vmovapd 64(%rcx,%rax,8), %zmm1
vsubpd (%rsi,%rax,8), %zmm0, %zmm0
vsubpd 64(%rsi,%rax,8), %zmm1, %zmm1
vdivpd 64(%rdx,%rax,8), %zmm1, %zmm1
vdivpd (%rdx,%rax,8), %zmm0, %zmm0
vmovapd %zmm0, (%rsi,%rax,8)
vmovapd %zmm1, 64(%rsi,%rax,8)
addl $16, %eax
movl 92(%rdi), %ecx
leal -15(%rcx), %edx
cmpl %edx, %eax
jl .LBB0_7vec x 32
# ...only vec loop body...
.LBB0_7: # %for.body
# =>This Inner Loop Header: Depth=1
cltq
movq (%rdi), %rcx
movq 8(%rdi), %rdx
movq 16(%rdi), %rsi
vmovapd (%rcx,%rax,8), %zmm0
vmovapd 64(%rcx,%rax,8), %zmm1
vmovapd 128(%rcx,%rax,8), %zmm2
vmovapd 192(%rcx,%rax,8), %zmm3
vsubpd 192(%rsi,%rax,8), %zmm3, %zmm3
vdivpd 192(%rdx,%rax,8), %zmm3, %zmm3
vsubpd (%rsi,%rax,8), %zmm0, %zmm0
vdivpd (%rdx,%rax,8), %zmm0, %zmm0
vsubpd 64(%rsi,%rax,8), %zmm1, %zmm1
vdivpd 64(%rdx,%rax,8), %zmm1, %zmm1
vsubpd 128(%rsi,%rax,8), %zmm2, %zmm2
vdivpd 128(%rdx,%rax,8), %zmm2, %zmm2
vmovapd %zmm2, 128(%rsi,%rax,8)
vmovapd %zmm1, 64(%rsi,%rax,8)
vmovapd %zmm0, (%rsi,%rax,8)
vmovapd %zmm3, 192(%rsi,%rax,8)
addl $32, %eax
movl 92(%rdi), %ecx
leal -31(%rcx), %edx
cmpl %edx, %eax
jl .LBB0_7exp
- same observations as for simple kernel
- some load/store ops are issued for ps instead of pd, technically wrong, might not be an issue (whole register is copied anyway)
nrn_state_hh: # @nrn_state_hh
# %bb.0:
pushq %r15 # | save callee registers on stack
pushq %r14 # |
pushq %rbx # |
movq %rdi, %r14 # copy mech in r14
movl 92(%rdi), %eax # mech->nodecount
leal -7(%rax), %ecx # mech->nodecount - 7
xorl %ebx, %ebx # set id = 0
testl %ecx, %ecx # |
jle .LBB0_1 # | mech->nodecount - 7 <= 0?
.p2align 4, 0x90
.LBB0_5: # %for.body
# =>This Inner Loop Header: Depth=1
movslq %ebx, %rbx # copy id and sign extend (this op could be avoided)
movq (%r14), %rax # mech->minf to rax | (these 3 ops could be outside the loop)
movq 8(%r14), %rcx # mech->mtau to rcx |
movq 16(%r14), %rdx # mech->m to rdx |
vmovapd (%rax,%rbx,8), %zmm0 # load packed double mech->minf[id]
vsubpd (%rdx,%rbx,8), %zmm0, %zmm0 # mech->minf[id] - load pd mech->m[id]
vdivpd (%rcx,%rbx,8), %zmm0, %zmm0 # (mech->minf[id] - mech->m[id]) / load pd mech->mtau[id]
vmovapd %zmm0, (%rdx,%rbx,8) # store pd to mech->m[id]
movq 16(%r14), %r15 # mech->m to rdx (this seems unnecessary)
vmovaps (%r15,%rbx,8), %zmm0 # move packed single into 1st arg for function call (technically should be vmovapd)
callq __svml_exp8@PLT # call to svml vec exp
vmovaps %zmm0, (%r15,%rbx,8) # store ps to mech->m[id] (technically should be vmovapd)
addl $8, %ebx # id += 8
movl 92(%r14), %eax # mech->nodecount | (these 2 ops could be outside the loop)
leal -7(%rax), %ecx # mech->nodecount - 7 |
cmpl %ecx, %ebx # |
jl .LBB0_5 # |id < mech->nodecount -7?
# ...scalar loop...gather
- same observations as for simple kernel
nrn_state_hh: # @nrn_state_hh
# %bb.0:
movl 92(%rdi), %ecx # mech->nodecount
leal -7(%rcx), %eax # mech->nodecount - 7
testl %eax, %eax # | mech->nodecount - 7 <= 0?
jle .LBB0_1 # |
# %bb.6: # %for.body.preheader
xorl %eax, %eax # set id = 0
.p2align 4, 0x90
.LBB0_7: # %for.body
# =>This Inner Loop Header: Depth=1
cltq # sign extend eax -> rax (this instruction could be avoid with size_t loop var)
movq 56(%rdi), %rcx # copy mech->nodeindex in rcx (this could be moved outside the loop)
vmovapd (%rcx,%rax,4), %ymm0 # load packed double mech->nodeindex[id] in ymm0 (8 x 32 bit)
movq 48(%rdi), %rcx # copy mech->voltage in rcx (this could be moved outside the loop)
kxnorw %k0, %k0, %k1 # set all bit mask to 1 in k1
vgatherdpd (%rcx,%ymm0,8), %zmm1 {%k1} # indirect load mech->voltage[node_id] to xmm0
movq (%rdi), %rcx # copy mech->minf to rcx
movq 16(%rdi), %rdx # copy mech->m to rdx
vaddpd (%rcx,%rax,8), %zmm1, %zmm0 # mech->voltage[node_id] + mech->minf[id]
vmovapd %zmm0, (%rdx,%rax,8) # store pd in mech->m[id]
addl $8, %eax # id +=8
movl 92(%rdi), %ecx # mech->nodecount | (these 2 ops could be outside the loop)
leal -7(%rcx), %edx # mech->nodecount - 7 |
cmpl %edx, %eax # |
jl .LBB0_7 # |id < mech->nodecount -7?
# ...scalar loop...ode
- mod file could be simplified, compiler does not simplify things like (a/b)/(1/b)
- same observations as for simple kernel
- some load/store ops are issued for ps instead of pd, technically wrong, might not be an issue (whole register is copied anyway)
- constants -1,0,1 allocated on the stack but there are free registers
- lots of register spilling
- a seemingly useless reg xor 0x0 instruction
nrn_state_hh: # @nrn_state_hh
# %bb.0:
pushq %r15 # | save callee registers on stack
pushq %r14 # |
pushq %rbx # |
subq $352, %rsp # imm = 0x160 (allocate 352 bytes on the stack)
movq %rdi, %r14 # copy mech in r14
movl 92(%rdi), %eax # mech->nodecount
leal -7(%rax), %ecx # mech->nodecount -7
xorl %ebx, %ebx # set id = 0
testl %ecx, %ecx # | mech->nodecount - 7 <= 0?
jle .LBB0_1 # |
# %bb.5: # %for.body.preheader
vbroadcastsd .LCPI0_0(%rip), %zmm0 # zmm0 = [-1.0E+0,-1.0E+0,-1.0E+0,-1.0E+0,-1.0E+0,-1.0E+0,-1.0E+0,-1.0E+0]
vmovups %zmm0, 256(%rsp) # 64-byte Spill, unaligned packed single store (technically should be vmovupd)
vbroadcastsd .LCPI0_1(%rip), %zmm0 # zmm0 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
vmovups %zmm0, 192(%rsp) # 64-byte Spill, unaligned packed single store (technically should be vmovupd)
vbroadcastsd .LCPI0_2(%rip), %zmm0 # zmm0 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0]
vmovupd %zmm0, 128(%rsp) # 64-byte Spill, unaligned packed double store
.p2align 4, 0x90
.LBB0_6: # %for.body
# =>This Inner Loop Header: Depth=1
movslq %ebx, %rbx # move id to rbx and sign extend
movq 16(%r14), %r15 # copy mech->m in r15
vmovapd (%r15,%rbx,8), %zmm3 # load packed double mech->m[id] | why
vmovupd %zmm3, 64(%rsp) # 64-byte Spill, store unaligned packed double mech->m[id] on the stack | ?
movq 8(%r14), %rax # copy mech->mtau in rax
vmovapd (%rax,%rbx,8), %zmm0 # load packed double mech->mtau[id]
vmovupd 256(%rsp), %zmm1 # 64-byte Reload, -1
vdivpd %zmm0, %zmm1, %zmm1 # -1/mech->mtau[id]
movq (%r14), %rax # copy mech->minf in rax
vmovupd 192(%rsp), %zmm2 # 64-byte Reload, 0 |
vxorpd (%rax,%rbx,8), %zmm2, %zmm2 # load pd mech->minf[id] ^ 0 | (this seems useless)
vdivpd %zmm0, %zmm2, %zmm0 # mech->minf[id] / mech->mtau[id]
vdivpd %zmm1, %zmm0, %zmm0 # (mech->minf[id] / mech->mtau[id]) / (-1/mech->mtau[id])
vsubpd %zmm3, %zmm0, %zmm0 # (mech->minf[id] / mech->mtau[id]) / (-1/mech->mtau[id]) - mech->m[id]
vmovupd %zmm0, (%rsp) # 64-byte Spill, store unaligned pd to stack (there are enough registers to avoid this)
vmulpd 72(%r14){1to8}, %zmm1, %zmm0 # broadcast mech->dt then * -1/mech->mtau[id]
callq __svml_exp8@PLT # call SVML
vmovupd 128(%rsp), %zmm1 # 64-byte Reload, load unaligned packed from stack, 1.0
vsubpd %zmm0, %zmm1, %zmm0 # 1.0 - exp(...)
vmulpd (%rsp), %zmm0, %zmm0 # 64-byte Folded Reload, uload pd from stack, (...) * (1 - exp(...))
vaddpd 64(%rsp), %zmm0, %zmm0 # 64-byte Folded Reload, uload pd from stack, mech->m[id] * (...)
vmovapd %zmm0, (%r15,%rbx,8) # aligned store pd to mech->m[id]
addl $8, %ebx # id+=8
movl 92(%r14), %eax # mech->nodecount | (these 2 ops could be outside the loop)
leal -7(%rax), %ecx # mech->nodecount - 7 |
cmpl %ecx, %ebx # | id < mech->nodecount -7?
jl .LBB0_6 # |
# ...scalar loop...
georgemitenkov
pramodk
As part of this ticket, we should look generated LLVM IR + assembly kernels and see if there are any obvious performance issues.
Here are steps:
.llfile with certain vector width but targeting different ISAs:Check all available architectures for specific target:
Generate
.llfile vector width of 8 once:And generate assembly kernels for different targets easily:
And generated assembly kernels: