Die size for zen CPU seems wrong to me

[ggael]

I think there is a misinterpretation of the data reported by this page for the zen2 & zen3 CPU families. Those chips are made of multiple dies, a few CCD (Compute Complex Die) and one big I/O Die (416mm^2 @12nm). One CCD can include up to 8 cores, and up to 8 CCD per chip. Some examples:

-	n CCD	core/CCD	die_size	core_units	die_size_per_core	I/O diesize
72F3	8	1	1064	8	133	416
7543	8	4	1064	32	33	416	https://www.techpowerup.com/cpu-specs/epyc-7543.c2379
7373	8	2	1064	16	67	416	https://www.techpowerup.com/cpu-specs/epyc-7373x.c2762
7313	4	4	740	16	46	416	https://www.techpowerup.com/cpu-specs/epyc-7313.c2389
7663	8	7	1064	56	19	416	https://www.techpowerup.com/cpu-specs/epyc-7663.c2376
7763	8	8	1064	64	17	416	https://www.techpowerup.com/cpu-specs/epyc-7763.c2373

As you can, depending on actual the configuration, two configs having the same number of cors can have a different the die_size_per_core.

[da-ekchajzer]

Thank you for your bug report.

I have seen that there was an issue with AMD data when reviewing the data for next version. If you look at the dev branch file, I have come up with new data (https://github.com/Boavizta/boaviztapi/blob/dev/boaviztapi/data/components/cpu_manufacture.csv).

Amd	zen2	2019	7	13.09	16	0.82	https://www.techarp.com/computer/amd-zen-3-tech-report/ (74mm2*core_units+125mm2)
Amd	zen2	2019	7	10.13	12	0.84	https://www.techarp.com/computer/amd-zen-3-tech-report/ (74mm2*core_units+125mm2)
Amd	zen2	2019	7	7.17	8	0.90	https://www.techarp.com/computer/amd-zen-3-tech-report/ (74mm2*core_units+125mm2)
Amd	zen2	2019	7	5.69	6	0.95	https://www.techarp.com/computer/amd-zen-3-tech-report/ (74mm2*core_units+125mm2)
Amd	zen3	2020	7	14.162	16	0.89	https://www.techarp.com/computer/amd-zen-3-tech-report/ (80.7mm2*core_units+125mm2)
Amd	zen3	2020	7	10.934	12	0.91	https://www.techarp.com/computer/amd-zen-3-tech-report/ (80.7mm2*core_units+125mm2)
Amd	zen3	2020	7	7.706	8	0.96	https://www.techarp.com/computer/amd-zen-3-tech-report/ (80.7mm2*core_units+125mm2)
Amd	zen3	2020	7	6.092	6	1.02	https://www.techarp.com/computer/amd-zen-3-tech-report/ (80.7mm2*core_units+125mm2)

https://www.techarp.com/computer/amd-zen-3-tech-report/

But from what I think you're saying, it is still not right :

• I/O die is reported to be 125mm2 for zen 2 and zen 3 in the above table, but from your source it is 416mm2

• Core Die (80.7mm2 for zen3 and 74mm2 for zen2) would not be the die per core, but the die per CCD ?

• If I understand it correctly, the die size of a CPU chip for AMD should be reported in the table for each nb of CCD for each generation. The core unit is not relevant for retrieving the total die size ?

Could you comment on those elements ?

[ggael]

Right, I think your source is for Ryzen proc, hence the huge difference for the IOD sizes.

• EPYC-zen2: 74*nb_cores/nb_cores_per_CCD + 416 (source: https://en.wikichip.org/wiki/amd/microarchitectures/zen_2)
• EPYC-zen3: 80.7*nb_cores/nb_cores_per_CCD + 416
• EPYC-zen4: 72*nb_cores/nb_cores_per_CCD + 397

However, neither nb_cores_per_CCD nor nb_CCD (=nb_cores/nb_cores_per_CCD) are known by the user. On the user side, the "simplest" would be to provide the actual CPU name.

I'm also unsure whether the current formula still stands for such multi-die CPUs (with multi-process sizes), and the production process size should probably also be taken into account since it is pretty clear that energy intensity is increasing with smaller process, but that's another topic !

[da-ekchajzer]

Thank you, it is clearer to me.

For now, we don't use different impact factors for different process. If you know any data that could help us to achieve this, you can discuss it here : https://github.com/Boavizta/boaviztapi/issues/135. However, the fix should allow the evaluation of multi-die CPUs for future version.

If we want to have a similar process for AMD and Intel, I believe that we should have a variable and fix die size fore each family :

• For Intel, the variable part will depend on the number of core of the CPU (nb_core) Fix and variable die size could be inferred with a simple linear regression from this file https://github.com/Boavizta/boaviztapi/blob/main/boaviztapi/data/components/cpu_manufacture.csv

• For AMD, the variable part will depend on the number of CCD (nb_CCD) Fix and variable die size are avaible in the sources we have begun to collect

Both nb_CCD and nb_core for each CPU name should be pre-recorded in the CPU file (https://github.com/Boavizta/boaviztapi/blob/main/boaviztapi/data/components/cpu_index.csv).

By doing so, users who want to compute data with custom nb_core or nb_CCD will be able to do so and user who only have their CPU won't have to know this information (complete for cpu file).

The main challenge is to get info on AMD and Intel CPU. We already have the sources, but we might need to develop a parser to get the data :

• https://github.com/Boavizta/boaviztapi/issues/131
• https://github.com/Boavizta/boaviztapi/issues/132

Does this solution make sense to you ?

[da-ekchajzer]

@ggael this bug should be fixed in the dev version thanks to our new approach on die completion. We now use this cpu_spec file : https://github.com/Boavizta/boaviztapi/blob/dev/boaviztapi/data/crowdsourcing/cpu_specs.csv to infer the die_sie.

If a specific CPU is not available in the file, we infer its die_size from available CPUs of the same family and/or number of cores.