Bread80 / RC2014-512K-ROM-512K-RAM-Board

Code to write/burn data to the RC2014 512k ROM 512k RAM board
http://bread80.com/?p=153
MIT License
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Suggestion to article about 512k ROM 512k RAM Board #1

Closed h0lmes closed 3 months ago

h0lmes commented 3 months ago

Hi!

Thanks for the article Understanding the RC2014 512k ROM 512k RAM Board! In the article you write:

There’s also one more port, $7c, which is used to enable (value 1) or disable (value 0) the banking mechanism. With the banking mechanism disabled logical banks 0 to 3 map directly to physical banks 0 to 3 which, you’ll remember, are ROM. This is important mechanism at boot up: the banking mechanism is disabled at reset, physical ROM banks $00 to $03 are paged in and the Z80 begins by executing boot code in physical ROM bank $00. (And this code will, if it has any sense, begin by mapping in some RAM so that it has a stack available if not an area for data storage).

I didn't find any logic which maps logical banks 0 to 3 to physical ROM banks 0 to 3 at reset. From what I see, at reset (e.g. when 74xx670 outputs are disabled) every logical bank (0-3) is mapped to a physical ROM bank 0 (CPU lines A14 and A15 are just ignored, MA14 and MA15 are pulled down by default).

It may be the case that I misunderstood something, so I kindly ask you to revise the article.

Bread80 commented 3 months ago

Hi Roman, Thank you for the correction. I’ve updated the article.

Mike

On May 5, 2024, Adrian Chadd @.***> wrote:

Hi!

In the article Understanding the RC2014 512k ROM 512k RAM Board http://bread80.com/?p=153 you write:

There’s also one more port, $7c, which is used to enable (value 1) or disable (value 0) the banking mechanism. With the banking mechanism disabled logical banks 0 to 3 map directly to physical banks 0 to 3 which, you’ll remember, are ROM. This is important mechanism at boot up: the banking mechanism is disabled at reset, physical ROM banks $00 to $03 are paged in and the Z80 begins by executing boot code in physical ROM bank $00. (And this code will, if it has any sense, begin by mapping in some RAM so that it has a stack available if not an area for data storage).

I didn't find any logic which maps logical banks 0 to 3 to physical ROM banks 0 to 3 at reset.  From what I see, at reset (e.g. when 74xx670 outputs are disabled) every logical bank (0-3) is mapped to a physical ROM bank 0 (CPU lines A14 and A15 are just ignored, MA14 and MA15 are pulled down by default).

It may be the case that I misunderstood something, so I kindly ask you to revise the article.

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