I have the Winbond W25Q32JV FLASH now working in SPI_FLASH_FAST_READ_DUAL_IO mode. According to the data sheet, this FLASH does not need dummy cycles in Fast Read Dual I/O mode. Instead of 8 dummy cycles (two byte) it needs one single Mode byte, correspondent to 4 cycles. The mode bits 5 and 4 should not equal to 2'b10, since this would change the behavior of the next read command.
Thank you very much for the feedback. I just received an IceBreaker with a Winbond W25Q128JV-DTR, that seems to be similar. I'll add some options to configure the number of dummy clocks.
With this chips we can go even faster (>4x) by
using QuadIO mode (if all the pins are wired to the FPGA, which is not the case on the IceStick for instance)
using DTR mode
using XIP mode (no longer need to send command, just send address and read data)
I'll do some tests...
Hello Bruno,
I have the Winbond W25Q32JV FLASH now working in SPI_FLASH_FAST_READ_DUAL_IO mode. According to the data sheet, this FLASH does not need dummy cycles in Fast Read Dual I/O mode. Instead of 8 dummy cycles (two byte) it needs one single Mode byte, correspondent to 4 cycles. The mode bits 5 and 4 should not equal to 2'b10, since this would change the behavior of the next read command.
From MappedSPIFlash.v, line 295:
clock_cnt <= 5'd28; // cmd: 8 clocks address: 12 clocks dummy: 8 clocks
If I set clock_cnt to 5'd24, everything is fine with my board. I tested with 16 MHz and 66 MHz clock frequency.
Regards, Bernd.