BrunoLevy / learn-fpga

Learning FPGA, yosys, nextpnr, and RISC-V
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How long it takes to synthetize the Toolchain in Arty 35T ? #45

Closed benitoss closed 3 years ago

benitoss commented 3 years ago

How long it takes to synthetize the blink example with the open toolchain in the Arty 35T ?

I am thinking to include the toolchain in IceStudio, but it's worth it if takes few seconds to synthetize the bitstream

Thanks and regards

mithro commented 3 years ago

You might want to try examples @ http://symbiflow-examples.rtfd.io/ for yourself. The currently developed Arty 35T based on Yosys + VPR is quite a bit slower than the ECP5 / iCE40 toolchain based on Yosys + nextpnr but it is getting better.

BTW There are plenty of easy ways to help improve the performance if you are a Python / C++ developer.

BrunoLevy commented 3 years ago

@mithro yes, I have seen it (and I have updated the symbiflow installation script based on the latest version).

@benitoss: the blink examples takes a few seconds to generate (there is not much difference between symbiflow and yosys/nextpnr-xilinx for such a small design).

Some stats for larger designs:

For a small core (femtorv32-quark RV32I, 1.2K LUTs, 400 FFs),

For a larger core (femtorv32-petitbateau RV32IMFC, 5K LUTs, 1K FFs)

But symbiflow quickly evolves, so it is a good idea to support both for now (and it is an even better idea - I think that @mithro won't disagree - to contribute to make symbiflow better/faster !!!).

benitoss commented 3 years ago

Thanks @mithro and @BrunoLevy for the answers. They are acceptable times for the yosys/nextpnr-xilinx option. I will try first with my board and later maybe I try to implement in ICeStudio + Apio

Thanks again. I close this issue

mithro commented 3 years ago

BTW Yosys + nextpnr-xilinx is currently unmaintained. It will eventually hopefully replaced with the nextpnr interchange format work in the future (which will be used for all of the Lattice, Xilinx and QuickLogic flows).