#5 Add placeholders for ice40 tutorial

BrunoLevy / learn-fpga

Learning FPGA, yosys, nextpnr, and RISC-V

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#5 Add placeholders for ice40 tutorial #6

Closed whatnick closed 3 years ago

whatnick commented 3 years ago

Closes #5 Signed-off-by: Tisham Dhar whatnickd@gmail.com

wuxx commented 3 years ago

some days ago I try to build it on my ice40up5k board, and it report failure, here is the error log on this commit, it seems that the SB_PLL40_CORE primitive don't allow use pin 35 (from BANK0) as the input source clk, but I reference the lattice technical document it says IO from BANK2 is not allowed. but pin 35 is from BANK0, it strange, may be the toolchain not support yet?

ERROR: PLL 'pll.pll' couldn't be placed anywhere, no suitable BEL found. Did you mean to use a PAD PLL ?

Info: Annotating ports with timing budgets for target frequency 12.00 MHz ERROR: cell type 'SB_PLL40_CORE' is unsupported (instantiated as 'pll.pll') 26 warnings, 2 errors Makefile:71: recipe for target 'ICEFEATHER.synth' failed

whatnick commented 3 years ago

some days ago I try to build it on my ice40up5k board, and it report failure, here is the error log on this commit, it seems that the SB_PLL40_CORE primitive don't allow use pin 35 (from BANK0) as the input source clk, but I reference the lattice technical document it says IO from BANK2 is not allowed. but pin 35 is from BANK0, it strange, may be the toolchain not support yet?

ERROR: PLL 'pll.pll' couldn't be placed anywhere, no suitable BEL found. Did you mean to use a PAD PLL ?

Info: Annotating ports with timing budgets for target frequency 12.00 MHz

ERROR: cell type 'SB_PLL40_CORE' is unsupported (instantiated as 'pll.pll') 26 warnings, 2 errors Makefile:71: recipe for target 'ICEFEATHER.synth' failed

My attempts are at exactly this road-block. Glad I have a few people following along and hopefully this PR can be merged as a first cut of WIP for up5k support.

wuxx commented 3 years ago

one solution is use the SB_PLL40_PAD instead of SB_PLL40_CORE

whatnick commented 3 years ago

Core PLL is used in a few places and will need a refactor.

BrunoLevy commented 3 years ago

added a PASSTHROUGH_PLL configuration in RTL/femtosoc_config.v and updated TUTORIALS/newboard.md accordingly
@whatnick, the instances of SB_PLL40_CORE that you found in Basic are not used in femtorv32 (there is a single instance, it is in RTL/DEVICES/femtopll.v)
From what I have read, it will probably work by replacing SB_PLL40_CORE with SB_PLL40_PAD in femtopll.v, would one of you guys give it a try ?

wuxx commented 3 years ago

ok，waiting for the commit :-)

wuxx commented 3 years ago

just try the latest code on my ice40up5k board,

the nexpnr told the max freq is about 20MHz, so I config the NRFFREQ to 18MHz Info: Max frequency for clock 'clk$glb_clk': 19.44 MHz (PASS at 12.00 MHz)
the reset pin is tied to GND
after programmed, open the serial port with baudrate 115200, but nothing show. did I miss something ?

wuxx commented 3 years ago

few days ago I work on the commit fbafcceb2a582bdfff59f643a6ea5785049956dc and do a modify with FemtoRV/FIRMWARE/LIBFEMTORV32/femtorv32.h -#define CONFIGWORD_DEVICES 3 +#define CONFIGWORD_DEVICES 2

it can succ log on serial port