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BrunoLevy / learn-fpga

Learning FPGA, yosys, nextpnr, and RISC-V
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Step 17 of FROM_BLINKER_TO_RISCV doesn't work for ULX3S #65

Open samontab opened 2 years ago

samontab commented 2 years ago

I was following FROM_BLINKER_TO_RISCV tutorial on a ULX3S, and it all started great but when trying to run step 17 on the board it says:

BOARDS/run_ulx3s.sh step17.v

step17.v:455: ERROR: Unimplemented compiler directive or undefined macro `CPU_FREQ.

I checked and indeed BOARDS/run_ulx3s.sh doesn't have CPU_FREQ defined while BOARDS/run_icestick.sh has it.

I tried defining it with some values, but then more issues appeared which I'm not sure how to solve:

ERROR: Module \femtoPLL' referenced in module\Clockworks' in cell `\genblk1.pll' is not part of the design.

Any help would be great.

BrunoLevy commented 2 years ago

Thank you for notifying this ! I have pushed a new version (-DULX3S was missing on command line), would you test it ?

BrunoLevy commented 2 years ago

(note: it will work until step 22, I still need to do something for SPI flash, will do that shortly...)

samontab commented 2 years ago

Thanks for the fix.

Most steps now work on the ULX3S but I had a couple of problems with verilator. Here's what I experienced:

Step 17 now works on the ULX3S correctly.

Step 18 also works on the ULX3S, but I found a small issue. If you're using screen as the terminal the output doesn't align correctly:

terminals

Step 19 doesn't work:

verilator -DBENCH -DBOARD_FREQ=12 -Wno-fatal --top-module SOC -cc -exe sim_main.cpp step18.v

%Error: step18.v:549:20: Define or directive not defined: '`CPU_FREQ'
  549 |       .clk_freq_hz(`CPU_FREQ*1000000),
      |                    ^~~~~~~~~
        step18.v:8:1: ... note: In file included from step18.v
%Error: step18.v:549:29: syntax error, unexpected '*', expecting TYPE-IDENTIFIER
  549 |       .clk_freq_hz(`CPU_FREQ*1000000),
      |                             ^
        step18.v:8:1: ... note: In file included from step18.v
%Error: Exiting due to 2 error(s)

Tried adding the same -DULX3S flag but it doesn't fix it.

Step 20 works until this part:

./run_verilator.sh step20.v

g++ -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -I../../../FIRMWARE/LIBFEMTORV32 -DSTANDALONE_FEMTOELF -std=gnu++14 -Os -c -o femto_elf.o ../../../FIRMWARE/LIBFEMTORV32/femto_elf.c g++ -I. -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -I../../../FIRMWARE/LIBFEMTORV32 -DSTANDALONE_FEMTOELF -std=gnu++14 -Os -c -o sim_main.o ../sim_main.cpp ../sim_main.cpp: In function ‘int main(int, char, char)’: ../sim_main.cpp:13:37: error: ‘class VSOC’ has no member named ‘SOCDOTRAMDOTMEM’ 13 | void simulated_RAM = (void)top.SOCDOTRAMDOTMEM; | ^~~~~~~ make: *** [VSOC.mk:66: sim_main.o] Error 1 ./run_verilator.sh: line 4: obj_dir/VSOC: No such file or directory

The board itself(BOARDS/run_ulx3s.sh step20.v) works fine. I was able to compile mandelbrot.S and it runs correctly on the ULX3S.

For Step 21 the same thing happened. It works fine on the ULX3S but verilator has the same error as in Step 20.

Step 22 is as you mention still not working:

> BOARDS/run_ulx3s.sh step22.v

ERROR: Module MappedSPIFlash' referenced in moduleSOC' in cell `SPIFlash' does not have a port named 'IO'.

BrunoLevy commented 2 years ago

Yes, I still need to port different things on the ULX3S. Main thing is the SPI Flash pin multiplexed that needs a special primitive, I will need to insert a layer between the SOC and the ULX3S, now working on doing that without making the whole design too complicated....

BrunoLevy commented 2 years ago