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BrunoLevy / learn-fpga

Learning FPGA, yosys, nextpnr, and RISC-V
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Building radiona_ulx3s_ex fails but the original LiteX python script works (ULX3s-12F) #79

Closed M4rkoHR closed 1 year ago

M4rkoHR commented 1 year ago

Building LiteX for the ULX3s-12F fails because it uses 58/56 DP16KD cells. I haven't been able to find a way to reduce this.

$ python3 -m boards.radiona_ulx3s_ex --device LFE5U-12F --sdram-module MT48LC16M16 --cpu-type femtorv --cpu-variant petitbateau --build --load --ecppack-compress --with-oled
.
.
.

5.48. Printing statistics.

=== radiona_ulx3s ===

   Number of wires:              13613
   Number of wire bits:          46570
   Number of public wires:       13613
   Number of public wire bits:   46570
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:              19147
     CCU2C                         856
     DP16KD                         58
     EHXPLLL                         2
     L6MUX21                       890
     LUT4                        10886
     MULT18X18D                      8
     ODDRX1F                         5
     PFUMX                        2646
     TRELLIS_DPR16X4               131
     TRELLIS_FF                   3646
     TRELLIS_IO                     19

5.49. Executing CHECK pass (checking for obvious problems).
Checking module radiona_ulx3s...
Found and reported 0 problems.

6. Executing JSON backend.

Warnings: 1 unique messages, 1 total
End of script. Logfile hash: 88b2206168, CPU: user 16.31s system 0.60s
Yosys 0.21+23 (git sha1 a9795c4fc, aarch64-apple-darwin20.2-clang 10.0.0-4ubuntu1 -fPIC -Os)
Time spent: 19% 7x techmap (3 sec), 16% 1x abc (3 sec), ...
Info: constraining clock net 'clk25' to 25.00 MHz

Info: Logic utilisation before packing:
Info:     Total LUT4s:     13384/24288    55%
Info:         logic LUTs:  10886/24288    44%
Info:         carry LUTs:   1712/24288     7%
Info:           RAM LUTs:    524/ 3036    17%
Info:          RAMW LUTs:    262/ 6072     4%

Info:      Total DFFs:      3646/24288    15%

Info: Packing IOs..
Info: pin 'wifi_gpio0$tr_io' constrained to Bel 'X0/Y26/PIOB'.
Info: pin 'user_led7$tr_io' constrained to Bel 'X0/Y20/PIOD'.
Info: pin 'user_led6$tr_io' constrained to Bel 'X0/Y17/PIOD'.
Info: pin 'user_led5$tr_io' constrained to Bel 'X0/Y23/PIOD'.
Info: pin 'user_led4$tr_io' constrained to Bel 'X0/Y17/PIOB'.
Info: pin 'user_led3$tr_io' constrained to Bel 'X0/Y17/PIOC'.
Info: pin 'user_led2$tr_io' constrained to Bel 'X0/Y17/PIOA'.
Info: pin 'user_led1$tr_io' constrained to Bel 'X0/Y14/PIOD'.
Info: pin 'user_led0$tr_io' constrained to Bel 'X0/Y14/PIOC'.
Info: spisdcard_mosi feeds TRELLIS_IO TRELLIS_IO_2, removing $nextpnr_ibuf spisdcard_mosi.
Info: pin 'TRELLIS_IO_2' constrained to Bel 'X0/Y32/PIOB'.
Info: pin 'spisdcard_miso$tr_io' constrained to Bel 'X0/Y29/PIOC'.
Info: spisdcard_cs_n feeds TRELLIS_IO TRELLIS_IO_1, removing $nextpnr_ibuf spisdcard_cs_n.
Info: pin 'TRELLIS_IO_1' constrained to Bel 'X0/Y32/PIOA'.
Info: spisdcard_clk feeds TRELLIS_IO TRELLIS_IO, removing $nextpnr_ibuf spisdcard_clk.
Info: pin 'TRELLIS_IO' constrained to Bel 'X0/Y26/PIOC'.
Info: pin 'serial_tx$tr_io' constrained to Bel 'X0/Y35/PIOC'.
Info: pin 'serial_rx$tr_io' constrained to Bel 'X0/Y44/PIOB'.
Info: pin 'sdram_we_n$tr_io' constrained to Bel 'X72/Y41/PIOC'.
Info: pin 'sdram_ras_n$tr_io' constrained to Bel 'X72/Y41/PIOB'.
Info: sdram_dq[15] feeds TRELLIS_IO TRELLIS_IO_18, removing $nextpnr_ibuf sdram_dq[15].
Info: pin 'TRELLIS_IO_18' constrained to Bel 'X72/Y11/PIOC'.
Info: sdram_dq[14] feeds TRELLIS_IO TRELLIS_IO_17, removing $nextpnr_ibuf sdram_dq[14].
Info: pin 'TRELLIS_IO_17' constrained to Bel 'X72/Y20/PIOC'.
Info: sdram_dq[13] feeds TRELLIS_IO TRELLIS_IO_16, removing $nextpnr_ibuf sdram_dq[13].
Info: pin 'TRELLIS_IO_16' constrained to Bel 'X72/Y5/PIOD'.
Info: sdram_dq[12] feeds TRELLIS_IO TRELLIS_IO_15, removing $nextpnr_ibuf sdram_dq[12].
Info: pin 'TRELLIS_IO_15' constrained to Bel 'X72/Y5/PIOC'.
Info: sdram_dq[11] feeds TRELLIS_IO TRELLIS_IO_14, removing $nextpnr_ibuf sdram_dq[11].
Info: pin 'TRELLIS_IO_14' constrained to Bel 'X72/Y14/PIOA'.
Info: sdram_dq[10] feeds TRELLIS_IO TRELLIS_IO_13, removing $nextpnr_ibuf sdram_dq[10].
Info: pin 'TRELLIS_IO_13' constrained to Bel 'X72/Y14/PIOB'.
Info: sdram_dq[9] feeds TRELLIS_IO TRELLIS_IO_12, removing $nextpnr_ibuf sdram_dq[9].
Info: pin 'TRELLIS_IO_12' constrained to Bel 'X72/Y14/PIOC'.
Info: sdram_dq[8] feeds TRELLIS_IO TRELLIS_IO_11, removing $nextpnr_ibuf sdram_dq[8].
Info: pin 'TRELLIS_IO_11' constrained to Bel 'X72/Y14/PIOD'.
Info: sdram_dq[7] feeds TRELLIS_IO TRELLIS_IO_10, removing $nextpnr_ibuf sdram_dq[7].
Info: pin 'TRELLIS_IO_10' constrained to Bel 'X72/Y41/PIOD'.
Info: sdram_dq[6] feeds TRELLIS_IO TRELLIS_IO_9, removing $nextpnr_ibuf sdram_dq[6].
Info: pin 'TRELLIS_IO_9' constrained to Bel 'X72/Y47/PIOD'.
Info: sdram_dq[5] feeds TRELLIS_IO TRELLIS_IO_8, removing $nextpnr_ibuf sdram_dq[5].
Info: pin 'TRELLIS_IO_8' constrained to Bel 'X72/Y44/PIOD'.
Info: sdram_dq[4] feeds TRELLIS_IO TRELLIS_IO_7, removing $nextpnr_ibuf sdram_dq[4].
Info: pin 'TRELLIS_IO_7' constrained to Bel 'X72/Y38/PIOD'.
Info: sdram_dq[3] feeds TRELLIS_IO TRELLIS_IO_6, removing $nextpnr_ibuf sdram_dq[3].
Info: pin 'TRELLIS_IO_6' constrained to Bel 'X72/Y32/PIOC'.
Info: sdram_dq[2] feeds TRELLIS_IO TRELLIS_IO_5, removing $nextpnr_ibuf sdram_dq[2].
Info: pin 'TRELLIS_IO_5' constrained to Bel 'X72/Y29/PIOD'.
Info: sdram_dq[1] feeds TRELLIS_IO TRELLIS_IO_4, removing $nextpnr_ibuf sdram_dq[1].
Info: pin 'TRELLIS_IO_4' constrained to Bel 'X72/Y29/PIOC'.
Info: sdram_dq[0] feeds TRELLIS_IO TRELLIS_IO_3, removing $nextpnr_ibuf sdram_dq[0].
Info: pin 'TRELLIS_IO_3' constrained to Bel 'X72/Y11/PIOD'.
Info: pin 'sdram_dm[1]$tr_io' constrained to Bel 'X72/Y17/PIOA'.
Info: pin 'sdram_dm[0]$tr_io' constrained to Bel 'X72/Y44/PIOC'.
Info: pin 'sdram_cs_n$tr_io' constrained to Bel 'X72/Y41/PIOA'.
Info: pin 'sdram_clock$tr_io' constrained to Bel 'X72/Y17/PIOB'.
Info: pin 'sdram_cke$tr_io' constrained to Bel 'X72/Y17/PIOC'.
Info: pin 'sdram_cas_n$tr_io' constrained to Bel 'X72/Y44/PIOA'.
Info: pin 'sdram_ba[1]$tr_io' constrained to Bel 'X72/Y38/PIOB'.
Info: pin 'sdram_ba[0]$tr_io' constrained to Bel 'X72/Y38/PIOC'.
Info: pin 'sdram_a[12]$tr_io' constrained to Bel 'X72/Y20/PIOA'.
Info: pin 'sdram_a[11]$tr_io' constrained to Bel 'X72/Y17/PIOD'.
Info: pin 'sdram_a[10]$tr_io' constrained to Bel 'X72/Y38/PIOA'.
Info: pin 'sdram_a[9]$tr_io' constrained to Bel 'X72/Y20/PIOB'.
Info: pin 'sdram_a[8]$tr_io' constrained to Bel 'X72/Y23/PIOA'.
Info: pin 'sdram_a[7]$tr_io' constrained to Bel 'X72/Y23/PIOC'.
Info: pin 'sdram_a[6]$tr_io' constrained to Bel 'X72/Y20/PIOD'.
Info: pin 'sdram_a[5]$tr_io' constrained to Bel 'X72/Y23/PIOB'.
Info: pin 'sdram_a[4]$tr_io' constrained to Bel 'X72/Y23/PIOD'.
Info: pin 'sdram_a[3]$tr_io' constrained to Bel 'X72/Y26/PIOC'.
Info: pin 'sdram_a[2]$tr_io' constrained to Bel 'X72/Y26/PIOA'.
Info: pin 'sdram_a[1]$tr_io' constrained to Bel 'X72/Y26/PIOD'.
Info: pin 'sdram_a[0]$tr_io' constrained to Bel 'X72/Y26/PIOB'.
Info: pin 'rst$tr_io' constrained to Bel 'X4/Y50/PIOA'.
Info: pin 'oled_spi_mosi$tr_io' constrained to Bel 'X0/Y47/PIOC'.
Info: pin 'oled_spi_clk$tr_io' constrained to Bel 'X0/Y47/PIOD'.
Info: pin 'oled_ctl_resn$tr_io' constrained to Bel 'X0/Y47/PIOB'.
Info: pin 'oled_ctl_dc$tr_io' constrained to Bel 'X0/Y47/PIOA'.
Info: pin 'oled_ctl_csn$tr_io' constrained to Bel 'X0/Y44/PIOA'.
Info: pin 'gpdi_data2_p$tr_io' constrained to Bel 'X40/Y0/PIOA'.
Info: pin 'gpdi_data1_p$tr_io' constrained to Bel 'X47/Y0/PIOA'.
Info: pin 'gpdi_data0_p$tr_io' constrained to Bel 'X56/Y0/PIOA'.
Info: pin 'gpdi_clk_p$tr_io' constrained to Bel 'X62/Y0/PIOA'.
Info: pin 'clk25$tr_io' constrained to Bel 'X0/Y26/PIOA'.
Info: IOLOGIC component OFS1P3BX_9 connected to PIO Bel X72/Y23/PIOA
Info: IOLOGIC component OFS1P3BX_8 connected to PIO Bel X72/Y23/PIOC
Info: IOLOGIC component OFS1P3BX_7 connected to PIO Bel X72/Y20/PIOD
Info: IOLOGIC component OFS1P3BX_6 connected to PIO Bel X72/Y23/PIOB
Info: IOLOGIC component OFS1P3BX_5 connected to PIO Bel X72/Y23/PIOD
Info: IOLOGIC component OFS1P3BX_4 connected to PIO Bel X72/Y26/PIOC
Info: IOLOGIC component OFS1P3BX_37 connected to PIO Bel X72/Y11/PIOC
Info: IOLOGIC component OFS1P3BX_36 connected to PIO Bel X72/Y20/PIOC
Info: IOLOGIC component OFS1P3BX_35 connected to PIO Bel X72/Y5/PIOD
Info: IOLOGIC component OFS1P3BX_34 connected to PIO Bel X72/Y5/PIOC
Info: IOLOGIC component OFS1P3BX_33 connected to PIO Bel X72/Y14/PIOA
Info: IOLOGIC component OFS1P3BX_32 connected to PIO Bel X72/Y14/PIOB
Info: IOLOGIC component OFS1P3BX_31 connected to PIO Bel X72/Y14/PIOC
Info: IOLOGIC component OFS1P3BX_30 connected to PIO Bel X72/Y14/PIOD
Info: IOLOGIC component OFS1P3BX_3 connected to PIO Bel X72/Y26/PIOA
Info: IOLOGIC component OFS1P3BX_29 connected to PIO Bel X72/Y41/PIOD
Info: IOLOGIC component OFS1P3BX_28 connected to PIO Bel X72/Y47/PIOD
Info: IOLOGIC component OFS1P3BX_27 connected to PIO Bel X72/Y44/PIOD
Info: IOLOGIC component OFS1P3BX_26 connected to PIO Bel X72/Y38/PIOD
Info: IOLOGIC component OFS1P3BX_25 connected to PIO Bel X72/Y32/PIOC
Info: IOLOGIC component OFS1P3BX_24 connected to PIO Bel X72/Y29/PIOD
Info: IOLOGIC component OFS1P3BX_23 connected to PIO Bel X72/Y29/PIOC
Info: IOLOGIC component OFS1P3BX_22 connected to PIO Bel X72/Y11/PIOD
Info: IOLOGIC component OFS1P3BX_21 connected to PIO Bel X72/Y17/PIOA
Info: IOLOGIC component OFS1P3BX_20 connected to PIO Bel X72/Y44/PIOC
Info: IOLOGIC component OFS1P3BX_2 connected to PIO Bel X72/Y26/PIOD
Info: IOLOGIC component OFS1P3BX_19 connected to PIO Bel X72/Y17/PIOC
Info: IOLOGIC component OFS1P3BX_18 connected to PIO Bel X72/Y41/PIOC
Info: IOLOGIC component OFS1P3BX_17 connected to PIO Bel X72/Y44/PIOA
Info: IOLOGIC component OFS1P3BX_16 connected to PIO Bel X72/Y41/PIOB
Info: IOLOGIC component OFS1P3BX_15 connected to PIO Bel X72/Y38/PIOB
Info: IOLOGIC component OFS1P3BX_14 connected to PIO Bel X72/Y38/PIOC
Info: IOLOGIC component OFS1P3BX_13 connected to PIO Bel X72/Y20/PIOA
Info: IOLOGIC component OFS1P3BX_12 connected to PIO Bel X72/Y17/PIOD
Info: IOLOGIC component OFS1P3BX_11 connected to PIO Bel X72/Y38/PIOA
Info: IOLOGIC component OFS1P3BX_10 connected to PIO Bel X72/Y20/PIOB
Info: IOLOGIC component OFS1P3BX_1 connected to PIO Bel X72/Y26/PIOB
Info: IOLOGIC component OFS1P3BX connected to PIO Bel X72/Y41/PIOA
Info: IOLOGIC component ODDRX1F_4 connected to PIO Bel X40/Y0/PIOA
Info: IOLOGIC component ODDRX1F_3 connected to PIO Bel X47/Y0/PIOA
Info: IOLOGIC component ODDRX1F_2 connected to PIO Bel X56/Y0/PIOA
Info: IOLOGIC component ODDRX1F_1 connected to PIO Bel X62/Y0/PIOA
Info: IOLOGIC component ODDRX1F connected to PIO Bel X72/Y17/PIOB
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info:     1628 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info:     Input frequency of PLL 'EHXPLLL_1' is constrained to 25.0 MHz
Info:     Derived frequency constraint of 25.0 MHz for net hdmi_clk
Info:     Derived frequency constraint of 125.0 MHz for net hdmi5x_clk
Info:     Derived frequency constraint of 500.0 MHz for net builder_basesoc_ecp5pll1_ecp5pll
Info:     Input frequency of PLL 'EHXPLLL' is constrained to 25.0 MHz
Info:     Derived frequency constraint of 50.0 MHz for net main_ecp5pll0_clkout0
Info:     Derived frequency constraint of 100.0 MHz for net main_ecp5pll0_clkout1
Info:     Derived frequency constraint of 100.0 MHz for net main_ecp5pll0_clkout2
Info:     Derived frequency constraint of 400.0 MHz for net builder_basesoc_ecp5pll0_ecp5pll
Info: Promoting globals...
Info:     promoting clock net main_ecp5pll0_clkout0 to global network
Info:     promoting clock net hdmi_clk to global network
Info:     promoting clock net main_ecp5pll0_clkout1 to global network
Info:     promoting clock net hdmi5x_clk to global network
Info:     promoting clock net main_ecp5pll0_clkout2 to global network
Info: Checksum: 0x760830a9

Info: Annotating ports with timing budgets for target frequency 12.00 MHz
Info: Checksum: 0x4679657e

Info: Device utilisation:
Info:             TRELLIS_IO:    65/  197    32%
Info:                   DCCA:     5/   56     8%
Info:                 DP16KD:    58/   56   103%
Info:             MULT18X18D:     8/   28    28%
Info:                 ALU54B:     0/   14     0%
Info:                EHXPLLL:     2/    2   100%
Info:                EXTREFB:     0/    1     0%
Info:                   DCUA:     0/    1     0%
Info:              PCSCLKDIV:     0/    2     0%
Info:                IOLOGIC:    39/  128    30%
Info:               SIOLOGIC:     4/   69     5%
Info:                    GSR:     0/    1     0%
Info:                  JTAGG:     0/    1     0%
Info:                   OSCG:     0/    1     0%
Info:                  SEDGA:     0/    1     0%
Info:                    DTR:     0/    1     0%
Info:                USRMCLK:     0/    1     0%
Info:                CLKDIVF:     0/    4     0%
Info:              ECLKSYNCB:     0/   10     0%
Info:                DLLDELD:     0/    8     0%
Info:                 DDRDLL:     0/    4     0%
Info:                DQSBUFM:     0/    8     0%
Info:        TRELLIS_ECLKBUF:     0/    8     0%
Info:           ECLKBRIDGECS:     0/    2     0%
Info:                   DCSC:     0/    2     0%
Info:             TRELLIS_FF:  3592/24288    14%
Info:           TRELLIS_COMB: 13730/24288    56%
Info:           TRELLIS_RAMW:   131/ 3036     4%

Info: Placed 110 cells based on constraints.
ERROR: Unable to place cell 'data_mem_grain1.0.0', no BELs remaining to implement cell type 'DP16KD'
0 warnings, 1 error
Traceback (most recent call last):
  File "/opt/homebrew/Cellar/python@3.10/3.10.8/Frameworks/Python.framework/Versions/3.10/lib/python3.10/runpy.py", line 196, in _run_module_as_main
    return _run_code(code, main_globals, None,
  File "/opt/homebrew/Cellar/python@3.10/3.10.8/Frameworks/Python.framework/Versions/3.10/lib/python3.10/runpy.py", line 86, in _run_code
    exec(code, run_globals)
  File "/Users/marko/Documents/GitHub/learn-fpga/LiteX/boards/radiona_ulx3s_ex.py", line 138, in <module>
    main()
  File "/Users/marko/Documents/GitHub/learn-fpga/LiteX/boards/radiona_ulx3s_ex.py", line 131, in main
    builder.build(**builder_kargs, run=args.build)
  File "/Users/marko/Documents/GitHub/LiteX/litex/litex/soc/integration/builder.py", line 366, in build
    vns = self.soc.build(build_dir=self.gateware_dir, **kwargs)
  File "/Users/marko/Documents/GitHub/LiteX/litex/litex/soc/integration/soc.py", line 1307, in build
    return self.platform.build(self, *args, **kwargs)
  File "/Users/marko/Documents/GitHub/LiteX/litex/litex/build/lattice/platform.py", line 48, in build
    return self.toolchain.build(self, *args, **kwargs)
  File "/Users/marko/Documents/GitHub/LiteX/litex/litex/build/lattice/trellis.py", line 67, in build
    return YosysNextPNRToolchain.build(self, platform, fragment, **kwargs)
  File "/Users/marko/Documents/GitHub/LiteX/litex/litex/build/yosys_nextpnr_toolchain.py", line 126, in build
    return GenericToolchain.build(self, platform, fragment, **kwargs)
  File "/Users/marko/Documents/GitHub/LiteX/litex/litex/build/generic_toolchain.py", line 118, in build
    self.run_script(script)
  File "/Users/marko/Documents/GitHub/LiteX/litex/litex/build/yosys_nextpnr_toolchain.py", line 231, in run_script
    raise OSError("Error occured during Yosys/Nextpnr's script execution.")
OSError: Error occured during Yosys/Nextpnr's script execution.

While building with same parameters from original LiteX source (litex-boards/litex_boards/targets/) I get this output (successful build):

$ python3 radiona_ulx3s.py --device LFE5U-12F --sdram-module MT48LC16M16 --cpu-type femtorv --cpu-variant petitbateau --build --load --ecppack-compress --with-oled
.
.
.
5.48. Printing statistics.

=== radiona_ulx3s ===

   Number of wires:              10455
   Number of wire bits:          33145
   Number of public wires:       10455
   Number of public wire bits:   33145
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:              14432
     CCU2C                         656
     DP16KD                         30
     EHXPLLL                         1
     L6MUX21                       767
     LUT4                         8412
     MULT18X18D                      8
     ODDRX1F                         1
     PFUMX                        2170
     TRELLIS_DPR16X4               108
     TRELLIS_FF                   2263
     TRELLIS_IO                     16

5.49. Executing CHECK pass (checking for obvious problems).
Checking module radiona_ulx3s...
Found and reported 0 problems.

6. Executing JSON backend.

Warnings: 1 unique messages, 1 total
End of script. Logfile hash: 096689b2b0, CPU: user 10.04s system 0.39s
Yosys 0.21+23 (git sha1 a9795c4fc, aarch64-apple-darwin20.2-clang 10.0.0-4ubuntu1 -fPIC -Os)
Time spent: 22% 7x techmap (2 sec), 20% 1x abc (2 sec), ...
Info: constraining clock net 'clk25' to 25.00 MHz

Info: Logic utilisation before packing:
Info:     Total LUT4s:     10372/24288    42%
Info:         logic LUTs:   8412/24288    34%
Info:         carry LUTs:   1312/24288     5%
Info:           RAM LUTs:    432/ 3036    14%
Info:          RAMW LUTs:    216/ 6072     3%

Info:      Total DFFs:      2263/24288     9%

Info: Packing IOs..
Info: pin 'wifi_gpio0$tr_io' constrained to Bel 'X0/Y26/PIOB'.
Info: pin 'user_led7$tr_io' constrained to Bel 'X0/Y20/PIOD'.
Info: pin 'user_led6$tr_io' constrained to Bel 'X0/Y17/PIOD'.
Info: pin 'user_led5$tr_io' constrained to Bel 'X0/Y23/PIOD'.
Info: pin 'user_led4$tr_io' constrained to Bel 'X0/Y17/PIOB'.
Info: pin 'user_led3$tr_io' constrained to Bel 'X0/Y17/PIOC'.
Info: pin 'user_led2$tr_io' constrained to Bel 'X0/Y17/PIOA'.
Info: pin 'user_led1$tr_io' constrained to Bel 'X0/Y14/PIOD'.
Info: pin 'user_led0$tr_io' constrained to Bel 'X0/Y14/PIOC'.
Info: pin 'serial_tx$tr_io' constrained to Bel 'X0/Y35/PIOC'.
Info: pin 'serial_rx$tr_io' constrained to Bel 'X0/Y44/PIOB'.
Info: pin 'sdram_we_n$tr_io' constrained to Bel 'X72/Y41/PIOC'.
Info: pin 'sdram_ras_n$tr_io' constrained to Bel 'X72/Y41/PIOB'.
Info: sdram_dq[15] feeds TRELLIS_IO TRELLIS_IO_15, removing $nextpnr_ibuf sdram_dq[15].
Info: pin 'TRELLIS_IO_15' constrained to Bel 'X72/Y11/PIOC'.
Info: sdram_dq[14] feeds TRELLIS_IO TRELLIS_IO_14, removing $nextpnr_ibuf sdram_dq[14].
Info: pin 'TRELLIS_IO_14' constrained to Bel 'X72/Y20/PIOC'.
Info: sdram_dq[13] feeds TRELLIS_IO TRELLIS_IO_13, removing $nextpnr_ibuf sdram_dq[13].
Info: pin 'TRELLIS_IO_13' constrained to Bel 'X72/Y5/PIOD'.
Info: sdram_dq[12] feeds TRELLIS_IO TRELLIS_IO_12, removing $nextpnr_ibuf sdram_dq[12].
Info: pin 'TRELLIS_IO_12' constrained to Bel 'X72/Y5/PIOC'.
Info: sdram_dq[11] feeds TRELLIS_IO TRELLIS_IO_11, removing $nextpnr_ibuf sdram_dq[11].
Info: pin 'TRELLIS_IO_11' constrained to Bel 'X72/Y14/PIOA'.
Info: sdram_dq[10] feeds TRELLIS_IO TRELLIS_IO_10, removing $nextpnr_ibuf sdram_dq[10].
Info: pin 'TRELLIS_IO_10' constrained to Bel 'X72/Y14/PIOB'.
Info: sdram_dq[9] feeds TRELLIS_IO TRELLIS_IO_9, removing $nextpnr_ibuf sdram_dq[9].
Info: pin 'TRELLIS_IO_9' constrained to Bel 'X72/Y14/PIOC'.
Info: sdram_dq[8] feeds TRELLIS_IO TRELLIS_IO_8, removing $nextpnr_ibuf sdram_dq[8].
Info: pin 'TRELLIS_IO_8' constrained to Bel 'X72/Y14/PIOD'.
Info: sdram_dq[7] feeds TRELLIS_IO TRELLIS_IO_7, removing $nextpnr_ibuf sdram_dq[7].
Info: pin 'TRELLIS_IO_7' constrained to Bel 'X72/Y41/PIOD'.
Info: sdram_dq[6] feeds TRELLIS_IO TRELLIS_IO_6, removing $nextpnr_ibuf sdram_dq[6].
Info: pin 'TRELLIS_IO_6' constrained to Bel 'X72/Y47/PIOD'.
Info: sdram_dq[5] feeds TRELLIS_IO TRELLIS_IO_5, removing $nextpnr_ibuf sdram_dq[5].
Info: pin 'TRELLIS_IO_5' constrained to Bel 'X72/Y44/PIOD'.
Info: sdram_dq[4] feeds TRELLIS_IO TRELLIS_IO_4, removing $nextpnr_ibuf sdram_dq[4].
Info: pin 'TRELLIS_IO_4' constrained to Bel 'X72/Y38/PIOD'.
Info: sdram_dq[3] feeds TRELLIS_IO TRELLIS_IO_3, removing $nextpnr_ibuf sdram_dq[3].
Info: pin 'TRELLIS_IO_3' constrained to Bel 'X72/Y32/PIOC'.
Info: sdram_dq[2] feeds TRELLIS_IO TRELLIS_IO_2, removing $nextpnr_ibuf sdram_dq[2].
Info: pin 'TRELLIS_IO_2' constrained to Bel 'X72/Y29/PIOD'.
Info: sdram_dq[1] feeds TRELLIS_IO TRELLIS_IO_1, removing $nextpnr_ibuf sdram_dq[1].
Info: pin 'TRELLIS_IO_1' constrained to Bel 'X72/Y29/PIOC'.
Info: sdram_dq[0] feeds TRELLIS_IO TRELLIS_IO, removing $nextpnr_ibuf sdram_dq[0].
Info: pin 'TRELLIS_IO' constrained to Bel 'X72/Y11/PIOD'.
Info: pin 'sdram_dm[1]$tr_io' constrained to Bel 'X72/Y17/PIOA'.
Info: pin 'sdram_dm[0]$tr_io' constrained to Bel 'X72/Y44/PIOC'.
Info: pin 'sdram_cs_n$tr_io' constrained to Bel 'X72/Y41/PIOA'.
Info: pin 'sdram_clock$tr_io' constrained to Bel 'X72/Y17/PIOB'.
Info: pin 'sdram_cke$tr_io' constrained to Bel 'X72/Y17/PIOC'.
Info: pin 'sdram_cas_n$tr_io' constrained to Bel 'X72/Y44/PIOA'.
Info: pin 'sdram_ba[1]$tr_io' constrained to Bel 'X72/Y38/PIOB'.
Info: pin 'sdram_ba[0]$tr_io' constrained to Bel 'X72/Y38/PIOC'.
Info: pin 'sdram_a[12]$tr_io' constrained to Bel 'X72/Y20/PIOA'.
Info: pin 'sdram_a[11]$tr_io' constrained to Bel 'X72/Y17/PIOD'.
Info: pin 'sdram_a[10]$tr_io' constrained to Bel 'X72/Y38/PIOA'.
Info: pin 'sdram_a[9]$tr_io' constrained to Bel 'X72/Y20/PIOB'.
Info: pin 'sdram_a[8]$tr_io' constrained to Bel 'X72/Y23/PIOA'.
Info: pin 'sdram_a[7]$tr_io' constrained to Bel 'X72/Y23/PIOC'.
Info: pin 'sdram_a[6]$tr_io' constrained to Bel 'X72/Y20/PIOD'.
Info: pin 'sdram_a[5]$tr_io' constrained to Bel 'X72/Y23/PIOB'.
Info: pin 'sdram_a[4]$tr_io' constrained to Bel 'X72/Y23/PIOD'.
Info: pin 'sdram_a[3]$tr_io' constrained to Bel 'X72/Y26/PIOC'.
Info: pin 'sdram_a[2]$tr_io' constrained to Bel 'X72/Y26/PIOA'.
Info: pin 'sdram_a[1]$tr_io' constrained to Bel 'X72/Y26/PIOD'.
Info: pin 'sdram_a[0]$tr_io' constrained to Bel 'X72/Y26/PIOB'.
Info: pin 'rst$tr_io' constrained to Bel 'X4/Y50/PIOA'.
Info: pin 'oled_spi_mosi$tr_io' constrained to Bel 'X0/Y47/PIOC'.
Info: pin 'oled_spi_clk$tr_io' constrained to Bel 'X0/Y47/PIOD'.
Info: pin 'oled_ctl_resn$tr_io' constrained to Bel 'X0/Y47/PIOB'.
Info: pin 'oled_ctl_dc$tr_io' constrained to Bel 'X0/Y47/PIOA'.
Info: pin 'oled_ctl_csn$tr_io' constrained to Bel 'X0/Y44/PIOA'.
Info: pin 'clk25$tr_io' constrained to Bel 'X0/Y26/PIOA'.
Info: IOLOGIC component OFS1P3BX_9 connected to PIO Bel X72/Y23/PIOA
Info: IOLOGIC component OFS1P3BX_8 connected to PIO Bel X72/Y23/PIOC
Info: IOLOGIC component OFS1P3BX_7 connected to PIO Bel X72/Y20/PIOD
Info: IOLOGIC component OFS1P3BX_6 connected to PIO Bel X72/Y23/PIOB
Info: IOLOGIC component OFS1P3BX_5 connected to PIO Bel X72/Y23/PIOD
Info: IOLOGIC component OFS1P3BX_4 connected to PIO Bel X72/Y26/PIOC
Info: IOLOGIC component OFS1P3BX_37 connected to PIO Bel X72/Y11/PIOC
Info: IOLOGIC component OFS1P3BX_36 connected to PIO Bel X72/Y20/PIOC
Info: IOLOGIC component OFS1P3BX_35 connected to PIO Bel X72/Y5/PIOD
Info: IOLOGIC component OFS1P3BX_34 connected to PIO Bel X72/Y5/PIOC
Info: IOLOGIC component OFS1P3BX_33 connected to PIO Bel X72/Y14/PIOA
Info: IOLOGIC component OFS1P3BX_32 connected to PIO Bel X72/Y14/PIOB
Info: IOLOGIC component OFS1P3BX_31 connected to PIO Bel X72/Y14/PIOC
Info: IOLOGIC component OFS1P3BX_30 connected to PIO Bel X72/Y14/PIOD
Info: IOLOGIC component OFS1P3BX_3 connected to PIO Bel X72/Y26/PIOA
Info: IOLOGIC component OFS1P3BX_29 connected to PIO Bel X72/Y41/PIOD
Info: IOLOGIC component OFS1P3BX_28 connected to PIO Bel X72/Y47/PIOD
Info: IOLOGIC component OFS1P3BX_27 connected to PIO Bel X72/Y44/PIOD
Info: IOLOGIC component OFS1P3BX_26 connected to PIO Bel X72/Y38/PIOD
Info: IOLOGIC component OFS1P3BX_25 connected to PIO Bel X72/Y32/PIOC
Info: IOLOGIC component OFS1P3BX_24 connected to PIO Bel X72/Y29/PIOD
Info: IOLOGIC component OFS1P3BX_23 connected to PIO Bel X72/Y29/PIOC
Info: IOLOGIC component OFS1P3BX_22 connected to PIO Bel X72/Y11/PIOD
Info: IOLOGIC component OFS1P3BX_21 connected to PIO Bel X72/Y17/PIOA
Info: IOLOGIC component OFS1P3BX_20 connected to PIO Bel X72/Y44/PIOC
Info: IOLOGIC component OFS1P3BX_2 connected to PIO Bel X72/Y26/PIOD
Info: IOLOGIC component OFS1P3BX_19 connected to PIO Bel X72/Y17/PIOC
Info: IOLOGIC component OFS1P3BX_18 connected to PIO Bel X72/Y41/PIOC
Info: IOLOGIC component OFS1P3BX_17 connected to PIO Bel X72/Y44/PIOA
Info: IOLOGIC component OFS1P3BX_16 connected to PIO Bel X72/Y41/PIOB
Info: IOLOGIC component OFS1P3BX_15 connected to PIO Bel X72/Y38/PIOB
Info: IOLOGIC component OFS1P3BX_14 connected to PIO Bel X72/Y38/PIOC
Info: IOLOGIC component OFS1P3BX_13 connected to PIO Bel X72/Y20/PIOA
Info: IOLOGIC component OFS1P3BX_12 connected to PIO Bel X72/Y17/PIOD
Info: IOLOGIC component OFS1P3BX_11 connected to PIO Bel X72/Y38/PIOA
Info: IOLOGIC component OFS1P3BX_10 connected to PIO Bel X72/Y20/PIOB
Info: IOLOGIC component OFS1P3BX_1 connected to PIO Bel X72/Y26/PIOB
Info: IOLOGIC component OFS1P3BX connected to PIO Bel X72/Y41/PIOA
Info: IOLOGIC component ODDRX1F connected to PIO Bel X72/Y17/PIOB
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info:     1167 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info:     Input frequency of PLL 'EHXPLLL' is constrained to 25.0 MHz
Info:     Derived frequency constraint of 50.0 MHz for net main_crg_clkout0
Info:     Derived frequency constraint of 50.0 MHz for net main_crg_clkout1
Info:     Derived frequency constraint of 400.0 MHz for net builder_basesoc_crg_ecp5pll
Info: Promoting globals...
Info:     promoting clock net main_crg_clkout0 to global network
Info:     promoting clock net main_crg_clkout1 to global network
Info: Checksum: 0x6f57faaa

Info: Annotating ports with timing budgets for target frequency 12.00 MHz
Info: Checksum: 0xf7ddbc03

Info: Device utilisation:
Info:             TRELLIS_IO:    57/  197    28%
Info:                   DCCA:     2/   56     3%
Info:                 DP16KD:    30/   56    53%
Info:             MULT18X18D:     8/   28    28%
Info:                 ALU54B:     0/   14     0%
Info:                EHXPLLL:     1/    2    50%
Info:                EXTREFB:     0/    1     0%
Info:                   DCUA:     0/    1     0%
Info:              PCSCLKDIV:     0/    2     0%
Info:                IOLOGIC:    39/  128    30%
Info:               SIOLOGIC:     0/   69     0%
Info:                    GSR:     0/    1     0%
Info:                  JTAGG:     0/    1     0%
Info:                   OSCG:     0/    1     0%
Info:                  SEDGA:     0/    1     0%
Info:                    DTR:     0/    1     0%
Info:                USRMCLK:     0/    1     0%
Info:                CLKDIVF:     0/    4     0%
Info:              ECLKSYNCB:     0/   10     0%
Info:                DLLDELD:     0/    8     0%
Info:                 DDRDLL:     0/    4     0%
Info:                DQSBUFM:     0/    8     0%
Info:        TRELLIS_ECLKBUF:     0/    8     0%
Info:           ECLKBRIDGECS:     0/    2     0%
Info:                   DCSC:     0/    2     0%
Info:             TRELLIS_FF:  2209/24288     9%
Info:           TRELLIS_COMB: 10590/24288    43%
Info:           TRELLIS_RAMW:   108/ 3036     3%
.
.
.

However, trying to build LiteOS with Makefile edited to point to the original LiteX successful build, I get these errors, as stated in #71 : 

 CC       boot.elf
/opt/homebrew/Cellar/riscv-gnu-toolchain/main/lib/gcc/riscv64-unknown-elf/12.2.0/../../../../riscv64-unknown-elf/bin/ld: /opt/homebrew/Cellar/riscv-gnu-toolchain/main/lib/gcc/riscv64-unknown-elf/12.2.0/rv32imac/ilp32/libgcc.a(_udivdi3.o): can't link soft-float modules with single-float modules
/opt/homebrew/Cellar/riscv-gnu-toolchain/main/lib/gcc/riscv64-unknown-elf/12.2.0/../../../../riscv64-unknown-elf/bin/ld: failed to merge target specific data of file /opt/homebrew/Cellar/riscv-gnu-toolchain/main/lib/gcc/riscv64-unknown-elf/12.2.0/rv32imac/ilp32/libgcc.a(_udivdi3.o)
/opt/homebrew/Cellar/riscv-gnu-toolchain/main/lib/gcc/riscv64-unknown-elf/12.2.0/../../../../riscv64-unknown-elf/bin/ld: /opt/homebrew/Cellar/riscv-gnu-toolchain/main/lib/gcc/riscv64-unknown-elf/12.2.0/rv32imac/ilp32/libgcc.a(_umoddi3.o): can't link soft-float modules with single-float modules
/opt/homebrew/Cellar/riscv-gnu-toolchain/main/lib/gcc/riscv64-unknown-elf/12.2.0/../../../../riscv64-unknown-elf/bin/ld: failed to merge target specific data of file /opt/homebrew/Cellar/riscv-gnu-toolchain/main/lib/gcc/riscv64-unknown-elf/12.2.0/rv32imac/ilp32/libgcc.a(_umoddi3.o)
/opt/homebrew/Cellar/riscv-gnu-toolchain/main/lib/gcc/riscv64-unknown-elf/12.2.0/../../../../riscv64-unknown-elf/bin/ld: /opt/homebrew/Cellar/riscv-gnu-toolchain/main/lib/gcc/riscv64-unknown-elf/12.2.0/rv32imac/ilp32/libgcc.a(_clz.o): can't link soft-float modules with single-float modules
/opt/homebrew/Cellar/riscv-gnu-toolchain/main/lib/gcc/riscv64-unknown-elf/12.2.0/../../../../riscv64-unknown-elf/bin/ld: failed to merge target specific data of file /opt/homebrew/Cellar/riscv-gnu-toolchain/main/lib/gcc/riscv64-unknown-elf/12.2.0/rv32imac/ilp32/libgcc.a(_clz.o)
/opt/homebrew/Cellar/riscv-gnu-toolchain/main/lib/gcc/riscv64-unknown-elf/12.2.0/../../../../riscv64-unknown-elf/bin/ld: warning: boot.elf has a LOAD segment with RWX permissions
/opt/homebrew/Cellar/riscv-gnu-toolchain/main/lib/gcc/riscv64-unknown-elf/12.2.0/../../../../riscv64-unknown-elf/bin/ld: /Users/marko/Documents/GitHub/LiteX/litex-boards/litex_boards/targets/build/radiona_ulx3s/software/liblitedram/liblitedram.a(sdram.o): in function `init_sequence':
/Users/marko/Documents/GitHub/LiteX/litex-boards/litex_boards/targets/build/radiona_ulx3s/software/include/generated/sdram_phy.h:90: undefined reference to `memtest'
/opt/homebrew/Cellar/riscv-gnu-toolchain/main/lib/gcc/riscv64-unknown-elf/12.2.0/../../../../riscv64-unknown-elf/bin/ld: /Users/marko/Documents/GitHub/LiteX/litex-boards/litex_boards/targets/build/radiona_ulx3s/software/include/generated/sdram_phy.h:96: undefined reference to `memspeed'
collect2: error: ld returned 1 exit status
make: *** [boot.elf] Error 1
M4rkoHR commented 1 year ago

Using flag --integrated-sram-size=0x1000 Fixes the compile error for radiona_ulx3s_ex, but the #71 issue still persists