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BrunoLevy / learn-fpga

Learning FPGA, yosys, nextpnr, and RISC-V
BSD 3-Clause "New" or "Revised" License
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FROM_BLINKER_TO_RISCV: step 19: verilator command does not work. #89

Closed wohlbier closed 1 year ago

wohlbier commented 1 year ago

The command suggested in step 19 $ verilator -DBENCH -DBOARD_FREQ=12 -Wno-fatal --top-module SOC -cc -exe sim_main.cpp step18.v doesn't work. It results in:

verilator -DBENCH -DBOARD_FREQ=12 -Wno-fatal --top-module SOC -cc -exe sim_main.cpp step18.v
%Error: step18.v:549:20: Define or directive not defined: '`CPU_FREQ'
  549 |       .clk_freq_hz(`CPU_FREQ*1000000),
      |                    ^~~~~~~~~
        step18.v:8:1: ... note: In file included from step18.v
%Error: step18.v:549:29: syntax error, unexpected '*', expecting TYPE-IDENTIFIER
  549 |       .clk_freq_hz(`CPU_FREQ*1000000),
      |                             ^
        step18.v:8:1: ... note: In file included from step18.v
%Error: Exiting due to 2 error(s)

When adding a definition for CPU_FREQ it becomes

verilator -DBENCH -DBOARD_FREQ=12 -DCPU_FREQ=45 -Wno-fatal --top-module SOC -cc -exe sim_main.cpp step18.v
%Warning-WIDTH: riscv_assembly.v:78:10: Bit extraction of array[1535:0] requires 11 bit index, not 30 bits.
                                      : ... In instance SOC.RAM
   78 |       MEM[memPC[31:2]] = {funct7, rs2, rs1, funct3, rd, opcode};
      |          ^
                step18.v:38:4: ... note: In file included from step18.v
                step18.v:8:1: ... note: In file included from step18.v
                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
%Warning-WIDTH: riscv_assembly.v:167:10: Bit extraction of array[1535:0] requires 11 bit index, not 30 bits.
                                       : ... In instance SOC.RAM
  167 |       MEM[memPC[31:2]] = {imm[11:0], rs1, funct3, rd, opcode};
      |          ^
                step18.v:38:4: ... note: In file included from step18.v
                step18.v:8:1: ... note: In file included from step18.v
%Warning-WIDTH: riscv_assembly.v:267:10: Bit extraction of array[1535:0] requires 11 bit index, not 30 bits.
                                       : ... In instance SOC.RAM
  267 |       MEM[memPC[31:2]] = {imm[20], imm[10:1], imm[11], imm[19:12], rd, opcode};
      |          ^
                step18.v:38:4: ... note: In file included from step18.v
                step18.v:8:1: ... note: In file included from step18.v
%Warning-WIDTH: riscv_assembly.v:304:10: Bit extraction of array[1535:0] requires 11 bit index, not 30 bits.
                                       : ... In instance SOC.RAM
  304 |       MEM[memPC[31:2]] = {imm[12],imm[10:5], rs2, rs1, funct3, imm[4:1], imm[11], opcode};
      |          ^
                step18.v:38:4: ... note: In file included from step18.v
                step18.v:8:1: ... note: In file included from step18.v
%Warning-WIDTH: riscv_assembly.v:374:10: Bit extraction of array[1535:0] requires 11 bit index, not 30 bits.
                                       : ... In instance SOC.RAM
  374 |       MEM[memPC[31:2]] = {imm[31:12], rd, opcode};
      |          ^
                step18.v:38:4: ... note: In file included from step18.v
                step18.v:8:1: ... note: In file included from step18.v
%Warning-WIDTH: riscv_assembly.v:459:10: Bit extraction of array[1535:0] requires 11 bit index, not 30 bits.
                                       : ... In instance SOC.RAM
  459 |       MEM[memPC[31:2]] = {imm[11:5], rs2, rs1, funct3, imm[4:0], opcode};
      |          ^
                step18.v:38:4: ... note: In file included from step18.v
                step18.v:8:1: ... note: In file included from step18.v
%Warning-WIDTH: riscv_assembly.v:507:10: Bit extraction of array[1535:0] requires 11 bit index, not 30 bits.
                                       : ... In instance SOC.RAM
  507 |       MEM[memPC[31:2]] = {4'b0000, pred, succ, 5'b00000, 3'b000, 5'b00000, 7'b1110011};
      |          ^
                step18.v:38:4: ... note: In file included from step18.v
                step18.v:8:1: ... note: In file included from step18.v
%Warning-WIDTH: riscv_assembly.v:514:10: Bit extraction of array[1535:0] requires 11 bit index, not 30 bits.
                                       : ... In instance SOC.RAM
  514 |       MEM[memPC[31:2]] = {4'b0000, 4'b0000, 4'b0000, 5'b00000, 3'b001, 5'b00000, 7'b1110011};
      |          ^
                step18.v:38:4: ... note: In file included from step18.v
                step18.v:8:1: ... note: In file included from step18.v
%Warning-WIDTH: riscv_assembly.v:521:10: Bit extraction of array[1535:0] requires 11 bit index, not 30 bits.
                                       : ... In instance SOC.RAM
  521 |       MEM[memPC[31:2]] = {12'b000000000000, 5'b00000, 3'b000, 5'b00000, 7'b1110011};
      |          ^
                step18.v:38:4: ... note: In file included from step18.v
                step18.v:8:1: ... note: In file included from step18.v
%Warning-WIDTH: riscv_assembly.v:528:10: Bit extraction of array[1535:0] requires 11 bit index, not 30 bits.
                                       : ... In instance SOC.RAM
  528 |       MEM[memPC[31:2]] = {12'b000000000001, 5'b00000, 3'b000, 5'b00000, 7'b1110011};
      |          ^
                step18.v:38:4: ... note: In file included from step18.v
                step18.v:8:1: ... note: In file included from step18.v
%Warning-WIDTH: riscv_assembly.v:538:10: Bit extraction of array[1535:0] requires 11 bit index, not 30 bits.
                                       : ... In instance SOC.RAM
  538 |       MEM[memPC[31:2]] = {csr, rs1, 3'b001, rd, 7'b1110011};
      |          ^
                step18.v:38:4: ... note: In file included from step18.v
                step18.v:8:1: ... note: In file included from step18.v
%Warning-WIDTH: riscv_assembly.v:548:10: Bit extraction of array[1535:0] requires 11 bit index, not 30 bits.
                                       : ... In instance SOC.RAM
  548 |       MEM[memPC[31:2]] = {csr, rs1, 3'b010, rd, 7'b1110011};
      |          ^
                step18.v:38:4: ... note: In file included from step18.v
                step18.v:8:1: ... note: In file included from step18.v
%Warning-WIDTH: riscv_assembly.v:558:10: Bit extraction of array[1535:0] requires 11 bit index, not 30 bits.
                                       : ... In instance SOC.RAM
  558 |       MEM[memPC[31:2]] = {csr, rs1, 3'b011, rd, 7'b1110011};
      |          ^
                step18.v:38:4: ... note: In file included from step18.v
                step18.v:8:1: ... note: In file included from step18.v
%Warning-WIDTH: riscv_assembly.v:568:10: Bit extraction of array[1535:0] requires 11 bit index, not 30 bits.
                                       : ... In instance SOC.RAM
  568 |       MEM[memPC[31:2]] = {csr, imm[4:0], 3'b101, rd, 7'b1110011};
      |          ^
                step18.v:38:4: ... note: In file included from step18.v
                step18.v:8:1: ... note: In file included from step18.v
%Warning-WIDTH: riscv_assembly.v:578:10: Bit extraction of array[1535:0] requires 11 bit index, not 30 bits.
                                       : ... In instance SOC.RAM
  578 |       MEM[memPC[31:2]] = {csr, imm[4:0], 3'b110, rd, 7'b1110011};
      |          ^
                step18.v:38:4: ... note: In file included from step18.v
                step18.v:8:1: ... note: In file included from step18.v
%Warning-WIDTH: riscv_assembly.v:588:10: Bit extraction of array[1535:0] requires 11 bit index, not 30 bits.
                                       : ... In instance SOC.RAM
  588 |       MEM[memPC[31:2]] = {csr, imm[4:0], 3'b111, rd, 7'b1110011};
      |          ^
                step18.v:38:4: ... note: In file included from step18.v
                step18.v:8:1: ... note: In file included from step18.v
%Warning-WIDTH: riscv_assembly.v:642:3: Logical Operator IF expects 1 bit on the If, but If's VARREF 'ASMerror' generates 32 bits.
                                      : ... In instance SOC.RAM
  642 |   if(ASMerror) $finish();
      |   ^~
                step18.v:38:4: ... note: In file included from step18.v
                step18.v:8:1: ... note: In file included from step18.v
%Warning-WIDTH: riscv_assembly.v:712:25: Operator SHIFTL expects 32 bits on the LHS, but LHS's SEL generates 1 bits.
                                       : ... In instance SOC.RAM
  712 |   LUI(rd,imm + (imm[11] << 12));  
      |                         ^~
                step18.v:38:4: ... note: In file included from step18.v
                step18.v:8:1: ... note: In file included from step18.v
%Warning-WIDTH: riscv_assembly.v:714:6: Operator TASKREF 'ADDI' expects 32 bits on the Function Argument, but Function Argument's SEL generates 12 bits.
                                      : ... In instance SOC.RAM
  714 |      ADDI(rd,rd,imm[11:0]);
      |      ^~~~
                step18.v:38:4: ... note: In file included from step18.v
                step18.v:8:1: ... note: In file included from step18.v
%Warning-WIDTH: riscv_assembly.v:724:6: Operator TASKREF 'JALR' expects 32 bits on the Function Argument, but Function Argument's SEL generates 12 bits.
                                      : ... In instance SOC.RAM
  724 |      JALR(x1, x6, offset[11:0]);
      |      ^~~~
                step18.v:38:4: ... note: In file included from step18.v
                step18.v:8:1: ... note: In file included from step18.v
%Warning-WIDTH: riscv_assembly.v:786:10: Bit extraction of array[1535:0] requires 11 bit index, not 30 bits.
                                       : ... In instance SOC.RAM
  786 |       MEM[memPC[31:2]] = w;
      |          ^
                step18.v:38:4: ... note: In file included from step18.v
                step18.v:8:1: ... note: In file included from step18.v
%Warning-WIDTH: riscv_assembly.v:797:10: Bit extraction of array[1535:0] requires 11 bit index, not 30 bits.
                                       : ... In instance SOC.RAM
  797 |       MEM[memPC[31:2]][ 7: 0] = b1;
      |          ^
                step18.v:38:4: ... note: In file included from step18.v
                step18.v:8:1: ... note: In file included from step18.v
%Warning-WIDTH: riscv_assembly.v:798:10: Bit extraction of array[1535:0] requires 11 bit index, not 30 bits.
                                       : ... In instance SOC.RAM
  798 |       MEM[memPC[31:2]][15: 8] = b2;
      |          ^
                step18.v:38:4: ... note: In file included from step18.v
                step18.v:8:1: ... note: In file included from step18.v
%Warning-WIDTH: riscv_assembly.v:799:10: Bit extraction of array[1535:0] requires 11 bit index, not 30 bits.
                                       : ... In instance SOC.RAM
  799 |       MEM[memPC[31:2]][23:16] = b3;
      |          ^
                step18.v:38:4: ... note: In file included from step18.v
                step18.v:8:1: ... note: In file included from step18.v
%Warning-WIDTH: riscv_assembly.v:800:10: Bit extraction of array[1535:0] requires 11 bit index, not 30 bits.
                                       : ... In instance SOC.RAM
  800 |       MEM[memPC[31:2]][31:24] = b4;            
      |          ^
                step18.v:38:4: ... note: In file included from step18.v
                step18.v:8:1: ... note: In file included from step18.v
%Warning-WIDTH: step18.v:206:26: Bit extraction of array[1535:0] requires 11 bit index, not 30 bits.
                               : ... In instance SOC.RAM
  206 |          mem_rdata <= MEM[word_addr];
      |                          ^
                step18.v:8:1: ... note: In file included from step18.v
%Warning-WIDTH: step18.v:208:27: Bit extraction of array[1535:0] requires 11 bit index, not 30 bits.
                               : ... In instance SOC.RAM
  208 |       if(mem_wmask[0]) MEM[word_addr][ 7:0 ] <= mem_wdata[ 7:0 ];
      |                           ^
                step18.v:8:1: ... note: In file included from step18.v
%Warning-WIDTH: step18.v:209:27: Bit extraction of array[1535:0] requires 11 bit index, not 30 bits.
                               : ... In instance SOC.RAM
  209 |       if(mem_wmask[1]) MEM[word_addr][15:8 ] <= mem_wdata[15:8 ];
      |                           ^
                step18.v:8:1: ... note: In file included from step18.v
%Warning-WIDTH: step18.v:210:27: Bit extraction of array[1535:0] requires 11 bit index, not 30 bits.
                               : ... In instance SOC.RAM
  210 |       if(mem_wmask[2]) MEM[word_addr][23:16] <= mem_wdata[23:16];
      |                           ^
                step18.v:8:1: ... note: In file included from step18.v
%Warning-WIDTH: step18.v:211:27: Bit extraction of array[1535:0] requires 11 bit index, not 30 bits.
                               : ... In instance SOC.RAM
  211 |       if(mem_wmask[3]) MEM[word_addr][31:24] <= mem_wdata[31:24];  
      |                           ^
                step18.v:8:1: ... note: In file included from step18.v
%Error: clockworks.v:88:9: Cannot find file containing module: 'femtoPLL'
   88 |         femtoPLL #(
      |         ^~~~~~~~
        step18.v:8:1: ... note: In file included from step18.v
%Error: clockworks.v:88:9: This may be because there's no search path specified with -I<dir>.
   88 |         femtoPLL #(
      |         ^~~~~~~~
        step18.v:8:1: ... note: In file included from step18.v
        ... Looked in:
             femtoPLL
             femtoPLL.v
             femtoPLL.sv
             obj_dir/femtoPLL
             obj_dir/femtoPLL.v
             obj_dir/femtoPLL.sv
%Warning-WIDTH: step18.v:540:8: Operator ASSIGNDLY expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'mem_wdata' generates 32 bits.
                              : ... In instance SOC
  540 |   LEDS <= mem_wdata;
      |        ^~
                step18.v:8:1: ... note: In file included from step18.v
%Error: Exiting due to 2 error(s)

I imagine that the script clears all of this up by including all sorts of other code, but the narrative should not suggest that the command will work.

JamesTimothyMeech commented 1 year ago

I have the same issue

wohlbier commented 1 year ago

I moved on. Everything else in the tutorial I was able to get to work.