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Buck008 / Transformer-Accelerator-Based-on-FPGA

You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size of the systolic array can be changed, now it is 16X16.
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Some questions about I/O #3

Open DurhackDa opened 3 months ago

DurhackDa commented 3 months ago

Hello, I've been studying what you've posted and I'm a student just starting to learn about the FPGA. When I follow the steps in the README, I encountered a problem with the I/O in the picture, if you have time could you help me to answer my doubts? Looking forward to hearing from you.

ViT
Buck008 commented 3 months ago

You should set design wrapper as the top 

------------------ Original ------------------ From: Da Cui @.> Date: Mon,Jul 22,2024 7:09 AM To: Buck008/Transformer-Accelerator-Based-on-FPGA @.> Cc: Subscribed @.***> Subject: Re: [Buck008/Transformer-Accelerator-Based-on-FPGA] Some questions aboutI/O (Issue #3)

Hello, I've been studying what you've posted and I'm a student just starting to learn about the FPGA. When I follow the steps in the README, I encountered a problem with the I/O in the picture, if you have time could you help me to answer my doubts? Looking forward to hearing from you. ViT.png (view on web)

— Reply to this email directly, view it on GitHub, or unsubscribe. You are receiving this because you are subscribed to this thread.Message ID: @.***>

DurhackDa commented 2 months ago

Hello, I successfully generated the bitstream file and loaded it into the PYNQ Z2 development board through Jupyter Notebook. However, when I run the python code in the project, the following error will be reported and cannot be modified correctly. I would like to ask have you encountered the same situation? Maybe there's something wrong with that part? Jupyter_error

DurhackDa commented 2 months ago

Hello, when generating a bitstream file, should I add all the verilog code to it? After I added and generated the bitstream file, the result of running the simulation code is as shown in the picture. It is different from yours. Did I do something wrong? I'm sorry to bother you. image

DurhackDa commented 2 months ago

I'm really sorry to bother you so often. Do I have to use Z1 to reproduce the steps for this project? Is it okay to use Z2 directly?

Buck008 commented 2 months ago

You can use any board, and you can test the project using CPP in vitis folder. You can follow my another open project https://github.com/Buck008/zcu104_test_pl_ddr to understand how to transfer data between PL and PS.

And the simulation is only for the matrix multiplication, not the SoC. You can't write the testbench for DDR or CPU by hand so just directly test that on board.

DurhackDa commented 2 months ago

Thank you very much for your reply. I strictly followed the steps in the readme to burn the bitstream file into the PYNQZ2 board, and then tested it with python and SDK test code respectively both encountered some problems, the picture is the problem I encountered in my SDK test. Is it possible to complete the test and see the output using SDK normally? Is it possible that I am doing some steps wrong? SDK_error

Thanks a lot for sharing, I'll try the test now with the vitis content and take a closer look at your other project to learn!