ByronPhung / combinational-logic-simulator

Generate truth tables for combinational logic circuits using Python.
MIT License
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Regarding Timing Information #8

Open Shivangp05 opened 3 years ago

Shivangp05 commented 3 years ago

If I want to add timing information in it like gate propagation delay only. The propagation delay information for the gate can be given in the same input file using one separate column. The output file will show the time taken to reach the output node considering gate delays in the path as shown in the image attached. image

Will it be possible to do so? And if it is possible then any suggestions from your side that what changes should I do in your code. It will be helpful for me.

Thank You.

ByronPhung commented 3 years ago

You would probably want to implement some sort of accumulator (i.e. literally just a variable tracking the total sum) and then add up the delay during each applicable gate processing. Since your use case is really simple and each gate has the same delay, you would probably just need to add the same number each time (as long as it passes through a gate).

Shivangp05 commented 3 years ago

Thank you for your valuable suggestion.